Yosinori Watanabe

Publication Activity (10 Years)

Years Active: 1991-2013
Publications (10 Years): 0

Top Topics

Combinatorial Auctions

Hardware Design

Modeling Framework

High Level Synthesis

Top Venues

Publications

Alex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe
Share with care: a quantitative evaluation of sharing approaches in high-level synthesis. DATE (2013)
Yosinori Watanabe, Stuart Swan
Clearing the clutter: Unified modeling and verification methodology for system level hardware design. MEMOCODE (2012)
Alex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe
Exploiting area/delay tradeoffs in high-level synthesis. DATE (2012)
Alex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe
Realistic performance-constrained pipelining in high-level synthesis. DATE (2011)
Luciano Lavagno, Alex Kondratyev, Yosinori Watanabe, Qiang Zhu, Mototsugu Fujii, Mitsuru Tatesawa, Noriyasu Nakayama
Incremental high-level synthesis. ASP-DAC (2010)
Gianpiero Cabodi, Luciano Lavagno, Marco Murciano, Alex Kondratyev, Yosinori Watanabe
Speeding-up heuristic allocation, scheduling and binding with SAT-based abstraction/refinement techniques. ACM Trans. Design Autom. Electr. Syst. 15 (2) (2010)
Eric Cheung, Xi Chen, Harry Hsieh, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe
Runtime deadlock analysis for system level design. Des. Autom. Embed. Syst. 13 (4) (2009)
Yosinori Watanabe
Examining Important Corner Cases: Verification of Interacting Architectural Components in System Designs. ACSD (2009)
Cong Liu, Alex Kondratyev, Yosinori Watanabe, Jörg Desel, Alberto L. Sangiovanni-Vincentelli
Schedulability Analysis of Petri Nets Based on Structural Properties. Fundam. Informaticae 86 (3) (2008)
Cong Liu, Alex Kondratyev, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli, Jörg Desel
Schedulability Analysis of Petri Nets Based on Structural Properties. ACSD (2006)
Shinjiro Kakita, Yosinori Watanabe, Douglas Densmore, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli
Functional Model Exploration for Multimedia Applications via Algebraic Operators. ACSD (2006)
Cong Liu, Alex Kondratyev, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli
A structural approach to quasi-static schedulability analysis of communicating concurrent programs. EMSOFT (2005)
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe
Quasi-static scheduling of independent tasks for reactive systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (10) (2005)
Luciano Lavagno, Claudio Passerone, Vishal Shah, Yosinori Watanabe
A Time Slice Based Scheduler Model for System Level Design. DATE (2005)
Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe
Simulation based deadlock analysis for system level designs. DAC (2005)
Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
Eliminating false positives in crosstalk noise analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (9) (2005)
Gianpiero Cabodi, Alex Kondratyev, Luciano Lavagno, Sergio Nocco, Stefano Quer, Yosinori Watanabe
A BMC-based formulation for the scheduling problem of hardware systems. Int. J. Softw. Tools Technol. Transf. 7 (2) (2005)
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Alexander Taubin, Yosinori Watanabe
Quasi-static Scheduling for Concurrent Architectures. Fundam. Informaticae 62 (2) (2004)
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
Logic of constraints: a quantitative performance and functional constraint formalism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (8) (2004)
Guang Yang, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Felice Balarin
Separation of concerns: overhead in modeling and efficient simulation techniques. EMSOFT (2004)
Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska
Eliminating False Positives in Crosstalk Noise Analysis. DATE (2004)
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
Automatic Generation of Simulation Monitors from Quantitative Constraint Formula. DATE (2003)
Bo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska
Gain-based technology mapping for discrete-size cell libraries. DAC (2003)
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
Verifying LOC based functional and performance constraints. HLDVT (2003)
Antonio G. Lomeña, Marisa Luisa López-Vallejo, Yosinori Watanabe, Alex Kondratyev
An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling. DATE (2003)
Felice Balarin, Yosinori Watanabe, Harry Hsieh, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli
Metropolis: An Integrated Electronic System Design Environment. Computer 36 (4) (2003)
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Yosinori Watanabe
Quasi-Static Scheduling for Concurrent Architectures. ACSD (2003)
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
Formal Verification for Embedded System Designs. Des. Autom. Embed. Syst. 8 (2-3) (2003)
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
Automatic trace analysis for logic of constraints. DAC (2003)
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
Case Studies of Model Checking for Embedded System Designs. ACSD (2003)
Gianpiero Cabodi, Sergio Nocco, Stefano Quer, Alex Kondratyev, Luciano Lavagno, Yosinori Watanabe
A BMC-formulation for the scheduling problem in highly constrained hardware Systems. Electron. Notes Theor. Comput. Sci. 89 (4) (2003)
Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
Temporofunctional crosstalk noise analysis. DAC (2003)
G. Arrigoni, L. Duchini, Claudio Passerone, Luciano Lavagno, Yosinori Watanabe
False Path Elimination in Quasi-Static Scheduling. DATE (2002)
Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe, Guang Yang
Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model. CODES (2002)
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe
Quasi-Static Scheduling of Independent Tasksfor Reactive Systems. ICATPN (2002)
Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto L. Sangiovanni-Vincentelli, Marco Sgroi, Yosinori Watanabe
Modeling and Designing Heterogeneous Systems. Concurrency and Hardware Design (2002)
Xi Chen, Fang Chen, Harry Hsieh, Felice Balarin, Yosinori Watanabe
Formal verification of embedded system designs at multiple levels of abstraction. HLDVT (2002)
Felice Balarin, Luciano Lavagno, Claudio Passerone, Yosinori Watanabe
Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis. EMSOFT (2002)
Claudio Passerone, Yosinori Watanabe, Luciano Lavagno
Generation of minimal size code for scheduling graphs. DATE (2001)
Felice Balarin, Jerry R. Burch, Luciano Lavagno, Yosinori Watanabe, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli
Constraints specification at higher levels of abstraction. HLDVT (2001)
Dirk-Jan Jongeneel, Yosinori Watanabe, Robert K. Brayton, Ralph H. J. M. Otten
Area and search space control for technology mapping. DAC (2000)
Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Marc Massot, Sandra Moral, Claudio Passerone, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli
Task generation and compile-time scheduling for mixed data-control embedded software. DAC (2000)
Marco Sgroi, Luciano Lavagno, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli
Quasi-Static Scheduling of Embedded Software Using Equal Conflict Nets. ICATPN (1999)
H. J. H. N. Kenter, Claudio Passerone, W. J. M. Smits, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli
Designing digital video systems: modeling and scheduling. CODES (1999)
Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness
Logic decomposition during technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (8) (1997)
Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton
Permissible functions for multioutput components in combinational logic optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15 (7) (1996)
Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinori Watanabe
A delay model for logic synthesis of continuously-sized networks. ICCAD (1995)
Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness
Logic decomposition during technology mapping. ICCAD (1995)
Yosinori Watanabe, Robert K. Brayton
State Minimization of Pseudo Non-Deterministic FSM's. EDAC-ETC-EUROASIC (1994)
Yosinori Watanabe, Lisa M. Guerra, Robert K. Brayton
Logic Optimization with Multi-Output Gates. ICCD (1993)
Yosinori Watanabe, Robert K. Brayton
Heuristic minimization of multiple-valued relations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (10) (1993)
Vigyan Singhal, Yosinori Watanabe, Robert K. Brayton
Heuristic Minimization of Synchronous Relations. ICCD (1993)
Yosinori Watanabe, Robert K. Brayton
The maximum set of permissible behaviors for FSM networks. ICCAD (1993)
Yosinori Watanabe, Robert K. Brayton
Incremental Synthesis for Engineering Changes. ICCD (1991)
Yosinori Watanabe, Robert K. Brayton
Heuristic Minimazation of Multiple-Valued Relations. ICCAD (1991)