Joel Grodstein

Publication Activity (10 Years)

Years Active: 1990-2011
Publications (10 Years): 0

Publications

Desta Tadesse, R. Iris Bahar, Joel Grodstein
Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems. J. Electron. Test. 27 (2) (2011)
Desta Tadesse, Joel Grodstein, R. Iris Bahar
AutoRex: An automated post-silicon clock tuning tool. ITC (2009)
Desta Tadesse, R. Iris Bahar, Joel Grodstein
Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. VTS (2008)
Desta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein
Accurate timing analysis using SAT and pattern-dependent delay models. DATE (2007)
Hui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein
Timing analysis for full-custom circuits using symbolic DC formulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (9) (2006)
R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein
Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (4) (2005)
Kundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein
RESTA: a robust and extendable symbolic timing analysis tool. ACM Great Lakes Symposium on VLSI (2004)
Joel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard A. Davies
Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor. ICCD (2003)
Hui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein
Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current. ICCD (2003)
Joel Grodstein, Rachid Rayess, Tad Truex, Linda Shattuck, Sue Lowell, Dan Bailey, David Bertucci, Gabriel P. Bischoff, Daniel E. Dever, Mike Gowan, Roy Lane, Brian Lilly, Krishna Nagalla, Rahul Shah, Emily Shriver, Shi-Huang Yin, Shannon V. Morton
Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU. ACM Great Lakes Symposium on VLSI (2002)
Hui-Yuan Song, R. Iris Bahar, Joel Grodstein
Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations. IWLS (2002)
Sribalan Santhanam, Allen J. Baum, David Bertucci, Mike Braganza, Kevin Broch, Todd Broch, James Burnette, Edward Chang, Kwong-Tak Chui, Dan Dobberpuhl, Paul M. Donahue, Joel Grodstein, Insung Kim, Daniel Murray, Mark H. Pearce, Amy Silveria, Dave Souydalay, Aaron Spink, Robert Stepanian, Anand Varadharajan, Vincent R. von Kaenel, Ricky Wen
A low-cost, 300-MHz, RISC CPU with attached media processor. IEEE J. Solid State Circuits 33 (11) (1998)
Joel Grodstein, Nick Rethman, N. Nassif
Static race verification for networks with reconvergent clocks. ICCD (1998)
Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness
Logic decomposition during technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (8) (1997)
Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinori Watanabe
A delay model for logic synthesis of continuously-sized networks. ICCAD (1995)
Eric Lehman, Yosinori Watanabe, Joel Grodstein, Heather Harkness
Logic decomposition during technology mapping. ICCAD (1995)
Joel Grodstein, Eric Lehman, Heather Harkness, Hervé J. Touati, Bill Grundmann
Optimal latch mapping and retiming within a tree. ICCAD (1994)
K. Kodandapani, Joel Grodstein, Antun Domic, Hervé J. Touati
A simple algorithm for fanout optimization using high-performance buffer libraries. ICCAD (1993)
Joel Grodstein, Nick Rethman, Rahul Razdan, Gabriel P. Bischoff
Automatic Detection of MOS Synchronizers for Timing Verification. ICCAD (1991)
Jengwei Pan, Larry L. Biro, Joel Grodstein, William J. Grundmann, Yao-Tsung Yen
Timing Verification on a 1.2M-Device Full-Custom CMOS Design. DAC (1991)
Joel Grodstein, Jengwei Pan, William J. Grundmann, Bruce Gieseke, Yao-Tsung Yen
Constraint Identification for Timing Verification. ICCAD (1990)
Joel Grodstein, Jim Montanaro, Susanne Marino
Race Detection for Two-Phase Systems. ICCAD (1990)