Kundan Nepal

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 19

Top Topics

Unanswered Questions

Activity Recognition

Top Venues

J. Electron. Test.

Publications

Alexander Coyle, Hui Jiang, Jennifer Dworak, Theodore W. Manikas, Kundan Nepal
Dual Use Circuitry for Early Failure Warning and Test. ISQED (2024)
Eslam Yassien, Yongjia Xu, Hui Jiang, Thach Nguyen, Jennifer Dworak, Theodore Manikas, Kundan Nepal
Harvesting Wasted Clock Cycles for Efficient Online Testing. ETS (2023)
Hui Jiang, Fanchen Zhang, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas
Increased Detection of Hard-to-Detect Stuck-at Faults during Scan Shift. J. Electron. Test. 39 (2) (2023)
Dulana Rupanetti, Hassan A. Salamy, Cheol-Hong Min, Kundan Nepal
Re-configurable, expandable, and cost-effective heterogeneous FPGA cluster approach for resource-constrained data analysis. Int. J. Parallel Emergent Distributed Syst. 37 (6) (2022)
Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, R. Iris Bahar
Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits. ITC (2021)
Soha Alhelaly, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Ping Gui, Alfred L. Crouch
3D Ring Oscillator Based Test Structures to Detect a Trojan Die in a 3D Die Stack in the Presence of Process Variations. IEEE Trans. Emerg. Top. Comput. 9 (2) (2021)
Dulana Rupanetti, Kundan Nepal, Hassan A. Salamy, Cheol-Hong Min
Cost-Effective, Re-Configurable Cluster Approach for Resource Constricted FPGA Based Machine Learning and AI Applications. CCWC (2020)
Milad Audi, William Frost, Jose Henriquez, Nathan Jones, Janssen Hang, Kundan Nepal
Low cost Brussels sprouts harvester for small farms. GHTC (2019)
Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Matan Segal, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar
Test Architecture for Fine Grained Capture Power Reduction. ICECS (2019)
Daniel Hellkamp, Kundan Nepal
True Three-Valued Ternary Content Addressable Memory Cell Based On Ambipolar Carbon Nanotube Transistors. J. Circuits Syst. Comput. 28 (5) (2019)
Jeremy Ziemer, Austin Stokes, Janssen Hang, Kundan Nepal
Low-cost instrumentation of high-tunnels for a small co-op farm. GHTC (2019)
Matthew Ward, Cheol-Hong Min, Hassan A. Salamy, Kundan Nepal
Dilated Temporal Convolutional Neural Network Architecture with Independent Component Layer for Human Activity Recognition. ICECS (2019)
Yi Sun, Fanchen Zhang, Hui Jiang, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar
Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack. J. Electron. Test. 35 (6) (2019)
Heath J. LeBlanc, Kundan Nepal, Greg S. Mowry, Alan Cheville
Tools for the 3Cs of Entrepreneurially Minded Learning (EML). FIE (2018)
Soha Alhelaly, Jennifer Dworak, Theodore W. Manikas, Ping Gui, Kundan Nepal, Alfred L. Crouch
Detecting a trojan die in 3D stacked integrated circuits. NATW (2017)
Noah Cornell, Kundan Nepal
Combinational hardware Trojan detection using logic implications. MWSCAS (2017)
Heath J. LeBlanc, Kundan Nepal, Greg S. Mowry
Stimulating curiosity and the ability to formulate technical questions in an electric circuits course using the question formulation technique (QFT). FIE (2017)
Fanchen Zhang, Yi Sun, Xi Shen, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, Ping Gui, R. Iris Bahar, Al Crouch, John C. Potter
Using Existing Reconfigurable Logic in 3D Die Stacks for Test. NATW (2016)
Kundan Nepal, Soha Alhelaly, Jennifer Dworak, R. Iris Bahar, Theodore W. Manikas, Ping Guikundan
Repairing a 3-D Die-Stack Using Available Programmable Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (5) (2015)
Kundan Nepal, Xi Shen, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar
Built-in Self-Repair in a 3D die stack using programmable logic. DFTS (2013)
Jennifer Dworak, Kundan Nepal, Nuno Alves, Yiwen Shi, Nicholas Imbriglia, R. Iris Bahar
Using implications to choose tests through suspect fault identification. ACM Trans. Design Autom. Electr. Syst. 18 (1) (2012)
Kundan Nepal
Ternary content addressable memory cells designed using ambipolar carbon nanotube transistors. NEWCAS (2012)
Maurice F. Aburdene, Kundan Nepal
Wow! linear systems and signal processing is fun! FIE (2011)
Carson Dunbar, Kundan Nepal
Using Platform FPGAs for Fault Emulation and Test-set Generation to Detect Stuck-at Faults. J. Comput. 6 (11) (2011)
Nuno Alves, Yiwen Shi, Nicholas Imbriglia, Jennifer Dworak, Kundan Nepal, R. Iris Bahar
Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis. ETS (2011)
Nuno Alves, Yiwen Shi, Jennifer Dworak, R. Iris Bahar, Kundan Nepal
Enhancing online error detection through area-efficient multi-site implications. VTS (2011)
Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar
Improving the testability and reliability of sequential circuits with invariant logic. ACM Great Lakes Symposium on VLSI (2010)
Nuno Alves, Alison Buben, Kundan Nepal, Jennifer Dworak, R. Iris Bahar
A Cost Effective Approach for Online Error Detection Using Invariant Relationships. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (5) (2010)
Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan Nepal
Compacting test vector sets via strategic use of implications. ICCAD (2009)
Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar
Detecting errors using multi-cycle invariance information. DATE (2009)
Kundan Nepal, Nuno Alves, Jennifer Dworak, R. Iris Bahar
Using Implications for Online Error Detection. ITC (2008)
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. DATE (2007)
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
Designing Nanoscale Logic Circuits Based on Markov Random Fields. J. Electron. Test. 23 (2-3) (2007)
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. IEEE Micro 26 (5) (2006)
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
Optimizing noise-immune nanoscale circuits using principles of Markov random fields. ACM Great Lakes Symposium on VLSI (2006)
Hui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein
Timing analysis for full-custom circuits using symbolic DC formulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (9) (2006)
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
Designing MRF based error correcting circuits for memory elements. DATE (2006)
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
Designing logic circuits for probabilistic computation in the presence of noise. DAC (2005)
R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein
Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (4) (2005)
Michelle Bovard, Matthew Gillette, Trishan R. de Lanerolle, Bozidar Marinkovic, Nhon H. Trinh, Peter Votto, David J. Ahlgren, Kundan Nepal, Amir Tamrakar
Design evolution of the Trinity College IGVC robot ALVIN. J. Field Robotics 21 (9) (2004)
Kundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein
RESTA: a robust and extendable symbolic timing analysis tool. ACM Great Lakes Symposium on VLSI (2004)