Improving the testability and reliability of sequential circuits with invariant logic.
Nuno AlvesKundan NepalJennifer DworakR. Iris BaharPublished in: ACM Great Lakes Symposium on VLSI (2010)
Keyphrases
- delay insensitive
- logic synthesis
- digital circuits
- logic circuits
- asynchronous circuits
- chip design
- logic programming
- random access memory
- high speed
- reliability analysis
- highly reliable
- classical logic
- automated reasoning
- affine invariant
- modal logic
- real time
- analog circuits
- defeasible logic
- test data generation
- truth table