Alexander Zaslavsky

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 5

Top Topics

Dynamic Random Access Memory

Top Venues

ACM Great Lakes Symposium on VLSI

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Andrei Beinarovich, Sergey Stepanov, Alexander Zaslavsky
Optimization of Discrete Parameters Using the Adaptive Gradient Method and Directed Evolution. CoRR (2024)
Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky
A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (3) (2018)
Xijing Han, Marco Donato, R. Iris Bahar, Alexander Zaslavsky, William R. Patterson
Design of Error-Resilient Logic Gates with Reinforcement Using Implications. ACM Great Lakes Symposium on VLSI (2016)
Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky
A fast simulator for the analysis of sub-threshold thermal noise transients. DAC (2016)
Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky
A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits. ACM Great Lakes Symposium on VLSI (2015)
Marco Donato, Fabio Cremona, Warren Jin, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky, Joseph L. Mundy
A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic. ACM Great Lakes Symposium on VLSI (2012)
Jing Wan, Cyrille Le Royer, Alexander Zaslavsky, Sorin Cristoloveanu
-FET used as 1-transistor high-speed DRAM. ESSDERC (2012)
Pooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices. ACM Great Lakes Symposium on VLSI (2010)
Hua Li, Joseph L. Mundy, William R. Patterson, Dimitrios Kazazis, Alexander Zaslavsky, R. Iris Bahar
Thermally-induced soft errors in nanoscale CMOS circuits. NANOARCH (2007)
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. DATE (2007)
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
Designing Nanoscale Logic Circuits Based on Markov Random Fields. J. Electron. Test. 23 (2-3) (2007)
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. IEEE Micro 26 (5) (2006)
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
Optimizing noise-immune nanoscale circuits using principles of Markov random fields. ACM Great Lakes Symposium on VLSI (2006)
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
Designing MRF based error correcting circuits for memory elements. DATE (2006)
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
Designing logic circuits for probabilistic computation in the presence of noise. DAC (2005)