Hassan A. Salamy

Publication Activity (10 Years)

Years Active: 2006-2022
Publications (10 Years): 14

Top Topics

Pheromone Trails

Activity Recognition

Embedded Systems

Convolutional Neural Network

Top Venues

Int. J. Parallel Emergent Distributed Syst.

J. Circuits Syst. Comput.

Publications

Dulana Rupanetti, Hassan A. Salamy, Cheol-Hong Min, Kundan Nepal
Re-configurable, expandable, and cost-effective heterogeneous FPGA cluster approach for resource-constrained data analysis. Int. J. Parallel Emergent Distributed Syst. 37 (6) (2022)
Matthew Ward, Kevin Malmsten, Hassan A. Salamy, Cheol-Hong Min
Data Balanced Bagging Ensemble of Convolutional- LSTM Neural Networks for Time Series Data Classification with an Imbalanced Dataset. ISCAS (2021)
Dulana Rupanetti, Hassan A. Salamy
Energy-Aware Task Migration Through Ant-Colony Optimization for Multiprocessors. UEMCON (2021)
Dulana Rupanetti, Hassan A. Salamy
Thermal and energy-aware utilisation management on MPSoC architectures. Int. J. Parallel Emergent Distributed Syst. 36 (5) (2021)
Hassan A. Salamy
Energy-Aware Schedules Under Chip Reliability Constraint for Multi-Processor Systems-on-a-Chip. J. Circuits Syst. Comput. 29 (9) (2020)
Dulana Rupanetti, Kundan Nepal, Hassan A. Salamy, Cheol-Hong Min
Cost-Effective, Re-Configurable Cluster Approach for Resource Constricted FPGA Based Machine Learning and AI Applications. CCWC (2020)
Dulana Rupanetti, Hassan A. Salamy
Task allocation, migration and scheduling for energy-efficient real-time multiprocessor architectures. J. Syst. Archit. 98 (2019)
Dulana Rupanetti, Hassan A. Salamy
Energy Efficient Scheduling with Task Migration on MPSoC Architectures. EIT (2019)
Dulana Rupanetti, Hassan A. Salamy
Thermal-Constrained. Energy-Aware Load Management on MPSoC Architectures. UEMCON (2019)
Matthew Ward, Cheol-Hong Min, Hassan A. Salamy, Kundan Nepal
Dilated Temporal Convolutional Neural Network Architecture with Independent Component Layer for Human Activity Recognition. ICECS (2019)
Hassan A. Salamy
An Effective Technique to Higher Throughput for Streaming Applications on an MPSoC. J. Comput. 14 (8) (2019)
Hassan A. Salamy, Semih Aslan
Pipelined-Scheduling of Multiple Embedded Applications on a Multi-Processor-SoC. J. Circuits Syst. Comput. 26 (3) (2017)
Hassan A. Salamy
An effective approach to schedule time reduction on multi-core embedded systems. Comput. Electr. Eng. 64 (2017)
Hassan A. Salamy, Mugdha Tasgaonkar
Energy efficient scheduling for a stream of applications on an MPSoC under throughput constraints. EIT (2016)
Hassan A. Salamy, Semih Aslan
Energy-aware schedule optimization on multicore systems. MWSCAS (2013)
Semih Aslan, Hassan A. Salamy, Jafar Saniie
Root Processing Engine. MWSCAS (2013)
Hassan A. Salamy, Semih Aslan, Divya Methukumalli
Task scheduling on multicores under energy and power constraints. CCECE (2013)
Hassan A. Salamy, J. Ramanujam
Storage Optimization through Offset Assignment with Variable Coalescing. ACM Trans. Embed. Comput. Syst. 11 (S1) (2012)
Hassan A. Salamy, J. Ramanujam
An ILP solution to address code generation for embedded applications on digital signal processors. ACM Trans. Design Autom. Electr. Syst. 17 (3) (2012)
Hassan A. Salamy, J. Ramanujam
Code Size Reduction for Array Intensive Applications on Digital Signal Processors. J. Circuits Syst. Comput. 21 (3) (2012)
Hassan A. Salamy, J. Ramanujam
An Effective Solution to Task Scheduling and Memory Partitioning for Multiprocessor System-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (5) (2012)
Hassan A. Salamy, Haidar Harmanani
An effective solution to thermal-aware test scheduling on network-on-chip using multiple clock rates. MWSCAS (2012)
Hassan A. Salamy
Minimizing address arithmetic instructions in embedded applications on DSPs. Comput. Electr. Eng. 38 (6) (2012)
Hassan A. Salamy
Compact code generation for embedded applications on digital signal processors. ICECS (2011)
Hassan A. Salamy, Haidar M. Harmanani
An optimal formulation for test scheduling network-on-chip using multiple clock rates. CCECE (2011)
Hassan A. Salamy, J. Ramanujam
A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip. HiPEAC (2009)
Hassan A. Salamy, J. Ramanujam
Storage optimization through code size reduction for digital signal processors. ESTIMedia (2008)
Hassan A. Salamy, J. Ramanujam
Optimal address register allocation for arrays in DSP applications. ESTIMedia (2008)
Haidar M. Harmanani, Hassan A. Salamy
A Simulated Annealing Algorithm for System-on-Chip Test Scheduling with, Power and Precedence Constraints. Int. J. Comput. Intell. Appl. 6 (4) (2006)
Haidar M. Harmanani, Hassan A. Salamy
Power-Constrained System-on-a-Chip Test Scheduling Using a Genetic Algorithm. J. Circuits Syst. Comput. 15 (3) (2006)
Hassan A. Salamy, J. Ramanujam
An Effective Heuristic for Simple Offset Assignment with Variable Coalescing. LCPC (2006)