Power-Constrained System-on-a-Chip Test Scheduling Using a Genetic Algorithm.
Haidar M. HarmananiHassan A. SalamyPublished in: J. Circuits Syst. Comput. (2006)
Keyphrases
- genetic algorithm
- built in self test
- scheduling problem
- power consumption
- scheduling algorithm
- fitness function
- high speed
- simulated annealing
- ibm power processor
- job shop scheduling problem
- multi objective
- genetic programming
- ant colony optimization
- genetic algorithm ga
- power management
- multithreading
- real time database systems
- round robin
- computational power
- neural network
- chip design
- resource constraints
- high density
- integrated circuit
- fuzzy logic
- evolutionary computation
- resource allocation
- metaheuristic
- test cases