A Simulated Annealing Algorithm for System-on-Chip Test Scheduling with, Power and Precedence Constraints.
Haidar M. HarmananiHassan A. SalamyPublished in: Int. J. Comput. Intell. Appl. (2006)
Keyphrases
- precedence constraints
- simulated annealing algorithm
- scheduling problem
- power consumption
- branch and bound algorithm
- simulated annealing
- precedence relations
- parallel machines
- release dates
- parallel processors
- approximation algorithms
- sequence dependent setup times
- vertex cover
- maximum lateness
- partial order
- global constraints
- single machine scheduling problem
- unit length
- search algorithm
- genetic algorithm
- partially ordered
- single machine
- identical machines
- flowshop
- np hard
- evolutionary algorithm
- worst case
- harmony search
- lower bound
- computational complexity
- mutation operator
- test problems
- premature convergence
- tabu search
- linear programming