Dilip K. Bhavsar

Publication Activity (10 Years)

Years Active: 1981-2011
Publications (10 Years): 0

Publications

Dilip K. Bhavsar, Steve Poehlman
Test access and the testability features of the Poulson multi-core Intel Itanium® processor. ITC (2011)
Dilip K. Bhavsar
Harmony Widget for X-free scan testing. VTS (2011)
Dilip K. Bhavsar
A Built-in Self-Test Method for Write-only Content Addressable Memories. VTS (2005)
Scott Erlanger, Dilip K. Bhavsar, Richard A. Davies
Testability Features of the Alpha 21364 Microprocessor. ITC (2003)
Joel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard A. Davies
Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor. ICCD (2003)
Dilip K. Bhavsar, Richard A. Davies
Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor. VTS (2002)
Dilip K. Bhavsar
Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester. VTS (2001)
Dilip K. Bhavsar, Rishan Tan
Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits. VLSI Design (2001)
Dilip K. Bhavsar
Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability. IEEE Des. Test Comput. 17 (2) (2000)
Dilip K. Bhavsar
ITC 99 Panels. IEEE Des. Test Comput. 16 (4) (1999)
Dilip K. Bhavsar
An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264. ITC (1999)
Dilip K. Bhavsar, David R. Akeson, Michael K. Gowan, Daniel B. Jackson
Testability access of the high speed test features in the Alpha 21264 microprocessor. ITC (1998)
Dilip K. Bhavsar, Ugonna Echeruo, David R. Akeson, William J. Bowhill
A highly testable and diagnosable fabrication process test chip. ITC (1998)
Dilip K. Bhavsar, Yervant Zorian
ITC 97 Panel Sessions. IEEE Des. Test Comput. 15 (1) (1998)
Dilip K. Bhavsar, John H. Edmondson
Alpha 21164 Testability Strategy. IEEE Des. Test Comput. 14 (1) (1997)
Dilip K. Bhavsar, John H. Edmondson
Testability Strategy of the ALPHA AXP 21164 Microprocessor. ITC (1994)
Dilip K. Bhavsar
An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanes. ITC (1991)
Dilip K. Bhavsar
Testing Interconnections to Static RAMs. IEEE Des. Test Comput. 8 (2) (1991)
Dilip K. Bhavsar
A New Economical Implementation for Scannable Flip-Flops in MOS. IEEE Des. Test 3 (3) (1986)
Dilip K. Bhavsar
"Concatenable Polydividers": Bit-Sliced LFSR Chips for Board Self-Test. ITC (1985)
Dilip K. Bhavsar, Balakrishnan Krishnamurthy
Can We Eliminate Fault Escape in Self-Testing by Polynomial Division (Signature Analysis) ? ITC (1984)
Dilip K. Bhavsar
Design For Test Calculus: An algorithm for DFT rules checking. DAC (1983)
Dilip K. Bhavsar, Richard W. Heckelman
Self-Testing by Polynomial Division. ITC (1981)