Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability.

Dilip K. Bhavsar

Published in: IEEE Des. Test Comput. (2000)

Keyphrases

test data generation
low cost
high speed
levels of abstraction
real time
genetic algorithm
higher level
test cases
data sets
access control
infrared
ad hoc networks
programmable logic