Mark H. Pearce

Publication Activity (10 Years)

Years Active: 1996-2003
Publications (10 Years): 0

Publications

Zongjian Chen, Daniel Murray, Steve Nishimoto, Mark H. Pearce, Max Oyker, Daniel Rodriguez, Robert Rogenmoser, Dongwook (Drew) Suh, Erik Supnet, Vincent von Kaenel, George Yiu
A 2× load/store pipe for a low-power 1-GHz embedded processor. IEEE J. Solid State Circuits 38 (11) (2003)
Sribalan Santhanam, Allen J. Baum, David Bertucci, Mike Braganza, Kevin Broch, Todd Broch, James Burnette, Edward Chang, Kwong-Tak Chui, Dan Dobberpuhl, Paul M. Donahue, Joel Grodstein, Insung Kim, Daniel Murray, Mark H. Pearce, Amy Silveria, Dave Souydalay, Aaron Spink, Robert Stepanian, Anand Varadharajan, Vincent R. von Kaenel, Ricky Wen
A low-cost, 300-MHz, RISC CPU with attached media processor. IEEE J. Solid State Circuits 33 (11) (1998)
James Montanaro, Richard T. Witek, Krishna Anne, Andrew J. Black, Elizabeth M. Cooper, Daniel W. Dobberpuhl, Paul M. Donahue, Jim Eno, Gregory W. Hoeppner, David Kruckemyer, Thomas H. Lee, Peter C. M. Lin, Liam Madden, Daniel Murray, Mark H. Pearce, Sribalan Santhanam, Kathryn J. Snyder, Ray Stephany, Stephen C. Thierauf
A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor. Digit. Tech. J. 9 (1) (1997)
James Montanaro, Richard T. Witek, Krishna Anne, Andrew J. Black, Elizabeth M. Cooper, Daniel W. Dobberpuhl, Paul M. Donahue, Jim Eno, Gregory W. Hoeppner, David Kruckemyer, Thomas H. Lee, Peter C. M. Lin, Liam Madden, Daniel Murray, Mark H. Pearce, Sribalan Santhanam, Kathryn J. Snyder, Ray Stephany, Stephen C. Thierauf
A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. IEEE J. Solid State Circuits 31 (11) (1996)