Vincent von Kaenel

Publication Activity (10 Years)

Years Active: 1995-2007
Publications (10 Years): 0

Publications

Brian Campbell, James Burnette, Naveen Javarappa, Vincent von Kaenel
Power-Efficient Dual-Supply 64kB L1 Caches in a 65nm CMOS Technology. CICC (2007)
Zongjian Chen, Priya Ananthanarayanan, Sukalp Biswas, Brian Campbell, Hao Chen, Shaishav Desai, Dominic Go, Rajat Goel, Vincent von Kaenel, Jason Kassoff, Fabian Klass, Weichun Ku, Tony Li, Jonathon Lin, Khurram Malik, Anup Mehta, Daniel Murray, Eric Shiu, Chris Shuler, Sribalan Santhanam, Greg Scott, Junji Sugisawa, Toshinari Takayanagi, Honkai John Tarn, Pradeep Trivedi, James Wang, Ricky Wen, John Yong
A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems. ISSCC (2007)
Vincent von Kaenel, Toshinari Takayanagi
Dual True Random Number Generators for Cryptographic Applications Embedded on a 200 Million Device Dual CPU SoC. CICC (2007)
Zongjian Chen, Daniel Murray, Steve Nishimoto, Mark H. Pearce, Max Oyker, Daniel Rodriguez, Robert Rogenmoser, Dongwook (Drew) Suh, Erik Supnet, Vincent von Kaenel, George Yiu
A 2× load/store pipe for a low-power 1-GHz embedded processor. IEEE J. Solid State Circuits 38 (11) (2003)
Daniel Aebischer, Henri J. Oguey, Vincent von Kaenel
A 2.1-MHz crystal oscillator time base with a current consumption under 500 nA. IEEE J. Solid State Circuits 32 (7) (1997)
Vincent von Kaenel, Daniel Aebischer, Christian Piguet, Evert Dijkstra
A 320 MHz, 1.5 mW@1.35 V CMOS PLL for microprocessor clock generation. IEEE J. Solid State Circuits 31 (11) (1996)
Christian Piguet, Jean-Marc Masgonty, Vincent von Kaenel, T. Schneider
Logic design for low-voltage/low-power CMOS circuits. ISLPD (1995)