Daniel Murray

Publication Activity (10 Years)

Years Active: 1996-2019
Publications (10 Years): 1

Top Topics

Fuzzy Logic Control

Fuzzy Reasoning

Digital Image Processing

Top Venues

Int. J. Knowl. Eng. Data Min.

Publications

Adnan Shaout, Daniel Murray, Abdelwahed Motwakel
Fuzzy logic image processing. Int. J. Knowl. Eng. Data Min. 6 (3) (2019)
Zongjian Chen, Priya Ananthanarayanan, Sukalp Biswas, Brian Campbell, Hao Chen, Shaishav Desai, Dominic Go, Rajat Goel, Vincent von Kaenel, Jason Kassoff, Fabian Klass, Weichun Ku, Tony Li, Jonathon Lin, Khurram Malik, Anup Mehta, Daniel Murray, Eric Shiu, Chris Shuler, Sribalan Santhanam, Greg Scott, Junji Sugisawa, Toshinari Takayanagi, Honkai John Tarn, Pradeep Trivedi, James Wang, Ricky Wen, John Yong
A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems. ISSCC (2007)
Daniel Murray, James Burnette, Brian Campbell, Mark Chung, Bruce Fernandes, Subhendra Ghosh, Rajat Goel, Greg Hess, Hang Huang, Zhibin Huang, Naveen Javarappa, Pradeep Kanapathipillai, Fabian Klass, Fang Liu, Anup Mehta, Yamini Modukuru, Nishant Nerurkar, Abhijit Radhakrishnan, Sribalan Santhanam, Junji Sugisawa, Shyam Sundar, Honkai John Tam, Ricky Wen, Eric Wu, Jung-Cheng Yeh, John Yong, Sanjay Zambare
Microprocessor Core. CICC (2007)
Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. IEEE J. Solid State Circuits 41 (1) (2006)
Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction. IEEE J. Solid State Circuits 40 (4) (2005)
Zongjian Chen, Daniel Murray, Steve Nishimoto, Mark H. Pearce, Max Oyker, Daniel Rodriguez, Robert Rogenmoser, Dongwook (Drew) Suh, Erik Supnet, Vincent von Kaenel, George Yiu
A 2× load/store pipe for a low-power 1-GHz embedded processor. IEEE J. Solid State Circuits 38 (11) (2003)
Sribalan Santhanam, Allen J. Baum, David Bertucci, Mike Braganza, Kevin Broch, Todd Broch, James Burnette, Edward Chang, Kwong-Tak Chui, Dan Dobberpuhl, Paul M. Donahue, Joel Grodstein, Insung Kim, Daniel Murray, Mark H. Pearce, Amy Silveria, Dave Souydalay, Aaron Spink, Robert Stepanian, Anand Varadharajan, Vincent R. von Kaenel, Ricky Wen
A low-cost, 300-MHz, RISC CPU with attached media processor. IEEE J. Solid State Circuits 33 (11) (1998)
James Montanaro, Richard T. Witek, Krishna Anne, Andrew J. Black, Elizabeth M. Cooper, Daniel W. Dobberpuhl, Paul M. Donahue, Jim Eno, Gregory W. Hoeppner, David Kruckemyer, Thomas H. Lee, Peter C. M. Lin, Liam Madden, Daniel Murray, Mark H. Pearce, Sribalan Santhanam, Kathryn J. Snyder, Ray Stephany, Stephen C. Thierauf
A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor. Digit. Tech. J. 9 (1) (1997)
James Montanaro, Richard T. Witek, Krishna Anne, Andrew J. Black, Elizabeth M. Cooper, Daniel W. Dobberpuhl, Paul M. Donahue, Jim Eno, Gregory W. Hoeppner, David Kruckemyer, Thomas H. Lee, Peter C. M. Lin, Liam Madden, Daniel Murray, Mark H. Pearce, Sribalan Santhanam, Kathryn J. Snyder, Ray Stephany, Stephen C. Thierauf
A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. IEEE J. Solid State Circuits 31 (11) (1996)