Zhanping Chen

Publication Activity (10 Years)

Years Active: 1997-2022
Publications (10 Years): 3

Top Topics

Close Proximity

Top Venues

IEEE J. Solid State Circuits

VLSI Technology and Circuits

Publications

Stafford Hutchins, Jiabo Li, Atresh Sanne, Zhanping Chen, Mohammad M. Hasan, Uddalak Bhattacharya, Eric Karl, Jaydeep P. Kulkarni
A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology. VLSI Technology and Circuits (2022)
Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Salil Manohar Rajarshi, Lei Jiang, Uddalak Bhattacharya
1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming. IEEE J. Solid State Circuits 52 (4) (2017)
Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, M. Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang
A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 51 (4) (2016)
Sarvesh H. Kulkarni, Zhanping Chen, Jun He, Lei Jiang, M. Brian Pedersen, Kevin Zhang
Bit Cell in 32 nm High-k Metal-Gate CMOS. IEEE J. Solid State Circuits 45 (4) (2010)
Fatih Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr
A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology. IEEE J. Solid State Circuits 44 (1) (2009)
Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr
A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. IEEE J. Solid State Circuits 43 (1) (2008)
Fatih Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr
A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology. ISSCC (2008)
Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. IEEE J. Solid State Circuits 41 (1) (2006)
Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction. IEEE J. Solid State Circuits 40 (4) (2005)
Liqiong Wei, Rongtian Zhang, Kaushik Roy, Zhanping Chen, David B. Janes
Vertically integrated SOI circuits for low-power and high-performance applications. IEEE Trans. Very Large Scale Integr. Syst. 10 (3) (2002)
Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy
IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions. IEEE Des. Test Comput. 19 (2) (2002)
Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy
IDDQ Testing for Deep Submicron ICs: Challenges and Solutions. LATW (2002)
James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. ISLPED (2001)
Zhanping Chen, Liqiong Wei, Kaushik Roy
testing of low-voltage CMOS circuits using leakage control techniques. IEEE Trans. Very Large Scale Integr. Syst. 9 (5) (2001)
Zhanping Chen, Kaushik Roy, Edwin K. P. Chong
Estimation of power dissipation using a novel power macromodelingtechnique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (11) (2000)
Zhanping Chen, Liqiong Wei, Kaushik Roy
On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques. ISQED (2000)
Kaushik Roy, Liqiong Wei, Zhanping Chen
Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications. ISCAS (1) (1999)
Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De
(MVT) CMOS Circuit Design Methodology for Low Power Applications. DAC (1999)
Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De
Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE Trans. Very Large Scale Integr. Syst. 7 (1) (1999)
Zhanping Chen, Kaushik Roy, Yibin Ye
Estimation of average switching power under accurate modeling of signal correlations. CICC (1998)
Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De
Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits. DAC (1998)
Zhanping Chen, Kaushik Roy, Tan-Li Chou
Efficient statistical approach to estimate power considering uncertain properties of primary inputs. IEEE Trans. Very Large Scale Integr. Syst. 6 (3) (1998)
Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. ISLPED (1998)
Zhanping Chen, Kaushik Roy
A Power Macromodeling Technique Based on Power Sensitivity. DAC (1998)
Zhanping Chen, Kaushik Roy, Edwin K. P. Chong
Estimation of power sensitivity in sequential circuits with power macromodeling application. ICCAD (1998)
Zhanping Chen, Kaushik Roy, Tan-Li Chou
Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs. ICCAD (1997)