Liqiong Wei

Publication Activity (10 Years)

Years Active: 1998-2019
Publications (10 Years): 2

Top Topics

Write Operations

Top Venues

Publications

Pulkit Jain, Umut Arslan, Meenakshi Sekhar, Blake C. Lin, Liqiong Wei, Tanaya Sahu, Juan Alzate-vinasco, Ajay Vangapaty, Mesut Meterelliyoz, Nathan Strutt, Albert B. Chen, Patrick Hentges, Pedro A. Quintero, Chris Connor, Oleg Golonzka, Kevin Fischer, Fatih Hamzaoglu
Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V. ISSCC (2019)
Liqiong Wei, Juan G. Alzate, Umut Arslan, Justin Brockman, Nilanjan Das, Kevin Fischer, Tahir Ghani, Oleg Golonzka, Patrick Hentges, Rawshan Jahan, Pulkit Jain, Blake C. Lin, Mesut Meterelliyoz, Jim O'Donnell, Conor Puls, Pedro A. Quintero, Tanaya Sahu, Meenakshi Sekhar, Ajay Vangapaty, Chris Wiegand, Fatih Hamzaoglu
A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique. ISSCC (2019)
Kyung-Hoae Koo, Liqiong Wei, John Keane, Uddalak Bhattacharya, Eric A. Karl, Kevin Zhang
high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist. VLSIC (2015)
Fatih Hamzaoglu, Yih Wang, Pramod Kolar, Liqiong Wei, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang
Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design. IEEE Des. Test Comput. 28 (1) (2011)
Yih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr
A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management. IEEE J. Solid State Circuits 45 (1) (2010)
Yih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr
A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management. ISSCC (2009)
Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr
A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. IEEE J. Solid State Circuits 43 (1) (2008)
Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Yih Zhang, Kevin Zhang, Mark Bohr
A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications. ISSCC (2007)
Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. DAC (2002)
Liqiong Wei, Rongtian Zhang, Kaushik Roy, Zhanping Chen, David B. Janes
Vertically integrated SOI circuits for low-power and high-performance applications. IEEE Trans. Very Large Scale Integr. Syst. 10 (3) (2002)
Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy
IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions. IEEE Des. Test Comput. 19 (2) (2002)
Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy
IDDQ Testing for Deep Submicron ICs: Challenges and Solutions. LATW (2002)
Zhanping Chen, Liqiong Wei, Kaushik Roy
testing of low-voltage CMOS circuits using leakage control techniques. IEEE Trans. Very Large Scale Integr. Syst. 9 (5) (2001)
Liqiong Wei, Kaushik Roy, Vivek De
Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs. VLSI Design (2000)
Liqiong Wei, Kaushik Roy, Cheng-Kok Koh
assignment and gate-sizing. CICC (2000)
Naran Sirisantana, Liqiong Wei, Kaushik Roy
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness. ICCD (2000)
Zhanping Chen, Liqiong Wei, Kaushik Roy
On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques. ISQED (2000)
Kaushik Roy, Liqiong Wei, Zhanping Chen
Multiple-Vdd multiple-Vth CMOS (MVCMOS) for low power applications. ISCAS (1) (1999)
Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De
(MVT) CMOS Circuit Design Methodology for Low Power Applications. DAC (1999)
Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De
Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE Trans. Very Large Scale Integr. Syst. 7 (1) (1999)
Liqiong Wei, Zhanping Chen, Mark Johnson, Kaushik Roy, Vivek De
Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits. DAC (1998)
Zhanping Chen, Mark Johnson, Liqiong Wei, Kaushik Roy
Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks. ISLPED (1998)