Yibin Ye

Publication Activity (10 Years)

Years Active: 1997-2024
Publications (10 Years): 8

Top Topics

Cognitive Radio

Wireless Ad Hoc Networks

Data Extraction

Top Venues

Comput. Electr. Eng.

IEEE Trans. Geosci. Remote. Sens.

Publications

Yibin Ye, Xichao Teng, Shuo Chen, Yijie Bian, Tao Tan, Zhang Li
3MOS: Multi-sources, Multi-resolutions, and Multi-scenes dataset for Optical-SAR image matching. CoRR (2024)
Yibin Ye, Qinwei Wang, Hong Zhao, Xichao Teng, Yijie Bian, Zhang Li
Fast and Robust Optical-to-SAR Remote Sensing Image Registration Using Region-Aware Phase Descriptor. IEEE Trans. Geosci. Remote. Sens. 62 (2024)
Yibin Ye, Shenggao Zhu, Jing Wang, Qi Du, Yezhang Yang, Dandan Tu, Lanjun Wang, Jiebo Luo
A unified scheme of text localization and structured data extraction for joint OCR and data mining. IEEE BigData (2018)
Yang Qin, Weihong Yang, Yibin Ye, Yao Shi
Analysis for TCP in data center networks: Outcast and Incast. J. Netw. Comput. Appl. 68 (2016)
Yang Qin, Xiaoxiong Zhong, Yuanyuan Yang, Li Li, Yibin Ye
Combined channel assignment and network coded opportunistic routing in cognitive radio networks. Comput. Electr. Eng. 52 (2016)
Yibin Ye, Yang Qin
QR factorization based Incremental Extreme Learning Machine with growth of hidden nodes. Pattern Recognit. Lett. 65 (2015)
Yang Qin, Li Li, Xiaoxiong Zhong, Yuanyuan Yang, Yibin Ye
Opportunistic routing with admission control in wireless ad hoc networks. Comput. Commun. 55 (2015)
Yang Qin, Xiaoxiong Zhong, Hao Jiang, Yibin Ye
An environment aware epidemic spreading model and immune strategy in complex networks. Appl. Math. Comput. 261 (2015)
Stefano Squartini, Yibin Ye, Francesco Piazza
Learning Capabilities of ELM-Trained Time-Varying Neural Networks. WIRN (2013)
Yibin Ye, Stefano Squartini, Francesco Piazza
Online sequential extreme learning machine in nonstationary environments. Neurocomputing 116 (2013)
Yibin Ye, Stefano Squartini, Francesco Piazza
On-Line Extreme Learning Machine for Training Time-Varying Neural Networks. ICIC (3) (2011)
Yibin Ye, Stefano Squartini, Francesco Piazza
ELM-based Algorithms for Nonstationary Volterra System Identification. WIRN (2011)
Yibin Ye, Stefano Squartini, Francesco Piazza
ELM-Based Time-Variant Neural Networks with Incremental Number of Output Basis Functions. ISNN (1) (2011)
Yibin Ye, Stefano Squartini, Francesco Piazza
A Group Selection Evolutionary Extreme Learning Machine approach for Time-Variant Neural Networks. WIRN (2010)
Yibin Ye, Stefano Squartini, Francesco Piazza
Incremental-Based Extreme Learning Machine Algorithms for Time-Variant Neural Networks. ICIC (1) (2010)
Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Borkar, Vivek K. De, Ali Keshavarzi
2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. IEEE J. Solid State Circuits 44 (1) (2009)
Muhammad M. Khellah, Nam-Sung Kim, Yibin Ye, Dinesh Somasekhar, Tanay Karnik, Nitin Borkar, Gunjan Pandya, Fatih Hamzaoglu, Tom Coan, Yih Wang, Kevin Zhang, Clair Webb, Vivek De
Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. IEEE J. Solid State Circuits 44 (4) (2009)
Yibin Ye, Mingmin Zhang, Huansen Li, Ruiying Jiang, Xing Tang, Zhigeng Pan
EasyFace: a realistic face modeling and facial animation authoring system. VRCAI (2009)
Zhigeng Pan, Huansen Li, Mingmin Zhang, Yibin Ye, Xi Cheng, Alvin Tang, Ruigang Yang
Photo Realistic 3D Cartoon Face Modeling Based on Active Shape Model. Trans. Edutainment 2 (2009)
Maged Ghoneima, Muhammad M. Khellah, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail, Vivek K. De
Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2008)
Dinesh Somasekhar, Yibin Ye, Paolo A. Aseron, Shih-Lien Lu, Muhammad M. Khellah, Jason Howard, Gregory Ruhl, Tanay Karnik, Shekhar Y. Borkar, Vivek De, Ali Keshavarzi
2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. ISSCC (2008)
Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Murad Sunna, James W. Tschanz, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De
SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. IEEE J. Solid State Circuits 42 (1) (2007)
Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Vivek De
Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. ISCAS (2006)
Muhammad M. Khellah, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Yibin Ye, James W. Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De
SRAM Building Block in 65nm CMOS. ISSCC (2006)
Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail
A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. ICCD (2005)
Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Vivek De
Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. ISCAS (1) (2005)
Arman Vassighi, Ali Keshavarzi, Siva G. Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De
Design optimizations for microprocessors at low temperature. DAC (2004)
Yibin Ye, Muhammad M. Khellah, Dinesh Somasekhar, Ali Farhang, Vivek De
technology using a bitline leakage reduction (BLR) technique. IEEE J. Solid State Circuits 38 (5) (2003)
James W. Tschanz, Siva G. Narendra, Yibin Ye, Bradley A. Bloechel, Shekhar Borkar, Vivek De
Dynamic sleep transistor and body bias for active leakage power control of microprocessors. IEEE J. Solid State Circuits 38 (11) (2003)
Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. DAC (2002)
Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva G. Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De
SRAM cells with full-swing single-ended bit line sensing for on-chip cache. IEEE Trans. Very Large Scale Integr. Syst. 10 (2) (2002)
Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar
CMOS. IEEE J. Solid State Circuits 37 (11) (2002)
Yibin Ye, Kaushik Roy
QSERL: quasi-static energy recovery logic. IEEE J. Solid State Circuits 36 (2) (2001)
Dinesh Somasekhar, Seung Hoon Choi, Kaushik Roy, Yibin Ye, Vivek De
Dynamic noise analysis in precharge-evaluate circuits. DAC (2000)
Yibin Ye, Kaushik Roy, Rolf Drechsler
Power Consumption in XOR-Based Circuits. ASP-DAC (1999)
Liqiong Wei, Zhanping Chen, Kaushik Roy, Yibin Ye, Vivek De
(MVT) CMOS Circuit Design Methodology for Low Power Applications. DAC (1999)
Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De
Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE Trans. Very Large Scale Integr. Syst. 7 (1) (1999)
Zhanping Chen, Kaushik Roy, Yibin Ye
Estimation of average switching power under accurate modeling of signal correlations. CICC (1998)
Yibin Ye, Kaushik Roy, Georgios I. Stamoulis
Quasi-static energy recovery logic and supply-clock generation circuits. ISLPED (1997)
Yibin Ye, Kaushik Roy
Efficient synthesis of AND/XOR networks. ASP-DAC (1997)
Yibin Ye, Kaushik Roy
A Graph-Based Synthesis Algorithm for AND/XOR Networks. DAC (1997)