Maged Ghoneima

Publication Activity (10 Years)

Years Active: 2003-2020
Publications (10 Years): 17

Top Topics

Depth Estimation

Binocular Vision

Top Venues

Microelectron. J.

Publications

Hossam O. Ahmed, Maged Ghoneima, Mohamed Dessouky
Reconfigurable Systolic-based Pyramidal Neuron Block for CNN Acceleration on FPGA. ICSET (2020)
Hossam O. Ahmed, Maged Ghoneima, Mohamed Dessouky
Systolic-based pyramidal neuron accelerator blocks for convolutional neural network. Microelectron. J. 89 (2019)
I. Mohamed Elzayat, M. Ahmed Saad, M. Mohamed Mostafa, R. Mahmoud Hassan, Hossam Abd El Munim, Maged Ghoneima, M. Saeed Darweesh, Hassan Mostafa
Real-Time Car Detection-Based Depth Estimation Using Mono Camera. ICM (2018)
Noha Shaarawy, Ahmed A. M. Emara, Ahmed M. El-Naggar, Mohammed E. Elbtity, Maged Ghoneima, Ahmed G. Radwan
Design and analysis of 2T2M hybrid CMOS-Memristor based RRAM. Microelectron. J. 73 (2018)
Ahmed Mahmoud, Loay Ehab, Mohamed Reda, Mostafa Abdelaleem, Hossam Abd El Munim, Maged Ghoneima, M. Saeed Darweesh, Hassan Mostafa
Real-Time Lane Detection-Based Line Segment Detection. NGCAS (2018)
Hossam O. Ahmed, Maged Ghoneima, Mohamed Dessouky
Pyramidal Neuron Architectures for AcceleratingDeep Neural Networks on FPGA. AHS (2018)
Hossam O. Ahmed, Maged Ghoneima, Mohamed Dessouky
High-Speed 2D Parallel MAC Unit Hardware Accelerator for Convolutional Neural Network. IntelliSys (1) (2018)
Taher Kourany, Maged Ghoneima, Emad Hegazi, Yehea Ismail
PASSIOT: A Pareto-optimal multi-objective optimization approach for synthesis of analog circuits using Sobol' indices-based engine. Integr. 58 (2017)
Youmna Magdy, Omar M. Shehata, Mohamed Abdelaziz, Maged Ghoneima, Farid A. Tolbah
Metaheuristic optimization in path planning of autonomous vehicles under the ATOM framework. ICVES (2017)
Islam S. M. Khalil, Ahmet Fatih Tabak, Abdelrahman Hosney, Abdallah Mohamed, Anke Klingner, Maged Ghoneima, Metin Sitti
Sperm-shaped magnetic microrobots: Fabrication using electrospinning, modeling, and characterization. ICRA (2016)
Mustafa Khairallah, Maged Ghoneima
Tile-Based Modular Architecture for Accelerating Homomorphic Function Evaluation on FPGA. IACR Cryptol. ePrint Arch. 2016 (2016)
Mostafa Shadoufa, Mohamed Mahmoud, Maged Ghoneima, Mohamed Dessouky
Optimization of the output power of a frequency-up conversion piezoelectric energy harvester. MWSCAS (2016)
Ahmed Emad, Mohamed A. E. Mahmoud, Maged Ghoneima, Mohamed Dessouky
Modeling and analysis of stretching strain in clamped-clamped beams for energy harvesting. MWSCAS (2016)
Taher Kourany, Maged Ghoneima, Emad Hegazi, Yehea Ismail
PASSIOT: A pareto-optimal multi-objective optimization approach for synthesis of analog circuits using sobol' indices-based engine. MWSCAS (2016)
Amr Lotfy, Maged Ghoneima, Mohamed Abdel-Moneum
A fast locking hybrid TDC-BB ADPLL utilizing proportional derivative digital loop filter and power gated DCO. ISCAS (2016)
Eslam Khafagy, Ahmed Hatab, Amr Rashed, Ahmed A. M. Emara, Maged Ghoneima
A fixed function 3D rendering hardware for mobile applications. ICM (2016)
Mustafa Khairallah, Maged Ghoneima
Tile-based modular architecture for accelerating homomorphic function evaluation on FPGA. MWSCAS (2016)
Mostafa Shadoufa, Ahmed Emad, Maged Ghoneima, Mohamed A. E. Mahmoud, Mohamed Dessouky
Structure optimization for efficient AlN piezoelectric energy harvesters. ICECS (2015)
Mustafa Khairallah, Maged Ghoneima
) for low-power on-chip crypto-systems. ISCAS (2015)
Ahmed A. M. Emara, Maged Ghoneima
A reference-less multilevel memristor based RRAM module. MWSCAS (2015)
Noha Shaarawy, Maged Ghoneima, Ahmed G. Radwan
2T2M memristor-based memory cell for higher stability RRAM modules. ISCAS (2015)
Ramy N. Tadros, Ahmed H. Abdelrahman, Maged Ghoneima, Yehea Ismail
A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme. ICEAC (2015)
Ramy N. Tadros, Abdelrahman H. Elsayed, Maged Ghoneima, Yehea I. Ismail
A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks. ISCAS (2014)
Abdelrahman H. Elsayed, Ramy N. Tadros, Maged Ghoneima, Yehea I. Ismail
Low-power all-digital manchester-encoding-based high-speed serdes transceiver for on-chip networks. ISCAS (2014)
Ezz El-Din O. Hussein, Sally Safwat, Maged Ghoneima, Yehea I. Ismail
A 16Gbps low power self-timed SerDes transceiver for multi-core communication. ISCAS (2012)
Moataz Abdelfattah, Maged Ghoneima, Yehea I. Ismail, Amr Lotfy, Mohamed Abdel-moneum, Nasser A. Kurd, Greg Taylor
Modeling the response of Bang-Bang digital PLLs to phase error perturbations. CICC (2012)
Ahmed El Kholy, Maged Ghoneima, Khaled Sharaf
A 0.8V 6.4µW compact mixed-signal front-end for neural implants. ISCAS (2012)
Moataz Abdelfattah, Maged Ghoneima, Yehea I. Ismail, Amr Lotfy, Mohamed Abdelsalam, Mohamed Abdel-moneum, Nasser A. Kurd, Greg Taylor
A novel digital loop filter architecture for bang-bang ADPLL. SoCC (2012)
Sally Safwat, Amr Lotfy, Maged Ghoneima, Yehea I. Ismail
A 5-10GHz low power bang-bang all digital PLL based on programmable digital loop filter. ISCAS (2012)
Mina Raymond, Maged Ghoneima, Yehea I. Ismail
A dynamic calibration scheme for on-chip process and temperature variations. ISCAS (2011)
Maged Ghoneima, Yong Lian, Gabriele Manganaro, Shahriar Mirabbasi, Christian Piguet, Wouter A. Serdijn
Guest Editorial Special Issue on ISCAS 2010. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2011)
Sally Safwat, Maged Ghoneima, Yehea I. Ismail
A design methodology for a low power bang-bang all digital PLL based on digital loop filter programmable coefficients. ICEAC (2011)
Amr M. Lotfy, Maged Ghoneima, Mohamed Abdel-Moneum
A novel power gated digitally controlled oscillator. ICEAC (2011)
Sally Safwat, Ezz El-Din O. Hussein, Maged Ghoneima, Yehea I. Ismail
A 12Gbps all digital low power SerDes transceiver for on-chip networking. ISCAS (2011)
Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
Serial-Link Bus: A Low-Power On-Chip Bus Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2009)
Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2009)
Maged Ghoneima, Muhammad M. Khellah, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail, Vivek K. De
Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2008)
Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme. VLSI Design 2007 (2007)
Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
Formal derivation of optimal active shielding for low-power on-chip buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (5) (2006)
Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2006)
Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
Reducing the data switching activity of serialized datastreams. ISCAS (2006)
Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De
Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ISLPED (2006)
Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De
Reducing the Data Switching Activity on Serial Link Buses. ISQED (2006)
Maged Ghoneima, Yehea I. Ismail
Optimum positioning of interleaved repeaters in bidirectional buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (3) (2005)
Noha H. Mahmoud, Maged Ghoneima, Yehea I. Ismail
Physical limitations on the bit-rate of on-chip interconnects. ACM Great Lakes Symposium on VLSI (2005)
Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail
A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. ICCD (2005)
Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Vivek De
Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. ISCAS (1) (2005)
Ja Chun Ku, Maged Ghoneima, Yehea I. Ismail
The importance of including thermal effects in estimating the effectiveness of power reduction techniques. CICC (2005)
Maged Ghoneima, Yehea I. Ismail
Accurate decoupling of capacitively coupled buses. ISCAS (4) (2005)
Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De
Serial-link bus: a low-power on-chip bus architecture. ICCAD (2005)
Maged Ghoneima, Ehsan Atoofian, Amirali Baniasadi, Yehea I. Ismail
Low-power prediction based data transfer architecture. CICC (2005)
Maged Ghoneima, Yehea I. Ismail
Effect of relative delay on the dissipated energy in coupled interconnects. ISCAS (2) (2004)
Maged Ghoneima, Yehea I. Ismail
Low power coupling-based encoding for on-chip buses. ISCAS (2) (2004)
Maged Ghoneima, Yehea I. Ismail
Formal derivation of optimal active shielding for low-power on-chip buses. ICCAD (2004)
Maged Ghoneima, Yehea I. Ismail
Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses. ISLPED (2004)
Maged Ghoneima, Yehea I. Ismail
Low-power on-chip bus architecture using dynamic relative delays. SoCC (2004)
Maged Ghoneima, Yehea I. Ismail
Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses. IEEE Trans. Very Large Scale Integr. Syst. 12 (12) (2004)
Maged Ghoneima, Yehea I. Ismail
Optimum positioning of interleaved repeaters In bidirectional buses. DAC (2003)