Reconfigurable Systolic-based Pyramidal Neuron Block for CNN Acceleration on FPGA.
Hossam O. AhmedMaged GhoneimaMohamed DessoukyPublished in: ICSET (2020)
Keyphrases
- systolic array
- reconfigurable architecture
- field programmable gate array
- data flow
- hardware implementation
- digital signal
- parallel architecture
- cellular neural networks
- neural network
- multiresolution
- low cost
- embedded systems
- reconfigurable hardware
- hardware design
- neural model
- software implementation
- digital signal processing
- block size
- efficient implementation
- single neuron
- signal processing
- high speed
- general purpose
- hardware software co design