Low-power on-chip bus architecture using dynamic relative delays.
Maged GhoneimaYehea I. IsmailPublished in: SoCC (2004)
Keyphrases
- low power
- high speed
- low cost
- mixed signal
- cmos technology
- vlsi architecture
- single chip
- nm technology
- power consumption
- signal processor
- low power consumption
- vlsi circuits
- cmos image sensor
- real time
- high power
- wireless transmission
- digital signal processing
- power dissipation
- low voltage
- logic circuits
- image sensor
- ultra low power
- power reduction
- vlsi implementation
- delay insensitive
- power saving