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A variation tolerant driving technique for all-digital self-timed 3-level signaling high-speed SerDes transceivers for on-chip networks.
Ramy N. Tadros
Abdelrahman H. Elsayed
Maged Ghoneima
Yehea I. Ismail
Published in:
ISCAS (2014)
Keyphrases
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high speed
low power
high bandwidth
mixed signal
high speed networks
low cost
low latency
real time
single chip
digital libraries
higher level
levels of abstraction
application specific
cmos image sensor
circuit design
high density
computer networks
complex networks
power consumption
neural network