A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors.
Muhammad M. KhellahMaged GhoneimaJames W. TschanzYibin YeNasser A. KurdJaved BarkatullahSrikanth NimmagaddaYehea I. IsmailPublished in: ICCD (2005)
Keyphrases
- high speed
- level parallelism
- single chip
- analog vlsi
- instruction set
- vlsi implementation
- management system
- low cost
- cmos image sensor
- low power
- floating point arithmetic
- real time
- energy minimization
- software architecture
- energy consumption
- floating point
- energy saving
- memory access
- class distribution
- parallel processing
- design methodology
- personal computer
- network on chip
- ibm power processor
- digital signal processors