Mark C. Johnson

Publication Activity (10 Years)

Years Active: 1996-2021
Publications (10 Years): 5

Top Topics

Student Progress

Multiple Intelligences

Error Criterion

Top Venues

ACM Great Lakes Symposium on VLSI

Publications

Xinkang Chen, Chun-Li Lo, Mark C. Johnson, Zhihong Chen, Sumeet Kumar Gupta
Modeling and Circuit Analysis of Interconnects with TaS2 Barrier/Liner. DRC (2021)
Jacob Covey, Mark C. Johnson
System-on-a-Chip Design as a Platform for Teaching Design and Design Flow Integration. ACM Great Lakes Symposium on VLSI (2019)
Todd Wild, Noah Chesnut, Gabriel Martini, Mark C. Johnson
Indiana bicentennial torch project: Trial by fire. MSE (2017)
Matthew Leiter, Lucas Goedde, Emily Fredette, Noah Chesnut, Matthew A. Swabey, Mark C. Johnson
Student use and assessment of System on Chip (SOC) prototyping resource. EWME (2016)
Matthew A. Swabey, Mark C. Johnson
Satisfying ABET criterion using an industrial Microelectronic Skills Incubator. MSE (2015)
Mark C. Johnson
Interactive application for learning RTL code structures. MSE (2011)
Mark C. Johnson, Eric P. Villasenor, Olga Krachina, Mithuna Thottethodi
Undergraduate dual-core prototyping and analysis of factors influencing student success on dual-core designs. MSE (2009)
Dongku Kang, Mark C. Johnson, Kaushik Roy
Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan. ISQED (2004)
Dongku Kang, Mark C. Johnson, Kaushik Roy
Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan. ICCD (2003)
Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy
Leakage control with efficient use of transistor stacks in single threshold CMOS. IEEE Trans. Very Large Scale Integr. Syst. 10 (1) (2002)
Mark C. Johnson
igital Design Education Infrastructure Using Multiple EDA Tool Vendors and Multiple Modes of Tool Access. MSE (2001)
Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
Models and algorithms for bounds on leakage in CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (6) (1999)
Mark C. Johnson, Dinesh Somasekhar, Kaushik Roy
Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS. DAC (1999)
Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De
Design and optimization of dual-threshold circuits for low-voltage low-power applications. IEEE Trans. Very Large Scale Integr. Syst. 7 (1) (1999)
Mark C. Johnson, Kaushik Roy
Datapath scheduling with multiple supply voltages and level converters. ACM Trans. Design Autom. Electr. Syst. 2 (3) (1997)
Mark C. Johnson, Kaushik Roy
Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource Constraints. ICCD (1996)