Manoj Sachdev

ORCID

Publication Activity (10 Years)

Years Active: 1993-2024
Publications (10 Years): 27

Top Venues

CICC

IEEE Trans. Circuits Syst. I Regul. Pap.

CoRR

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Sheida Gohardehi, Manoj Sachdev
Low-Power Row Driver for Digitally Driven OLEDoS Microdisplay. IEEE Trans. Circuits Syst. I Regul. Pap. 71 (6) (2024)
Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev
Enhancing Strong PUF Security With Nonmonotonic Response Quantization. IEEE Trans. Very Large Scale Integr. Syst. 31 (1) (2023)
Yugal Maheshwari, Manoj Sachdev
VLFF - A Very Low-power Flip-flop with only Two Clock Transistors. SOCC (2023)
Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev
Enhancing Strong PUF Security with Non-monotonic Response Quantization. CoRR (2022)
Kleber Stangherlin, Manoj Sachdev
Design and Implementation of a Secure RISC-V Microprocessor. IEEE Trans. Very Large Scale Integr. Syst. 30 (11) (2022)
Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev
Design Exploration and Security Assessment of PUF-on-PUF Implementations. CoRR (2022)
Kleber Stangherlin, Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev
Secure and Lightweight Strong PUF Challenge Obfuscation with Keyed Non-linear FSR. CoRR (2022)
Kleber Stangherlin, Manoj Sachdev
Design and Implementation of a Secure RISC-V Microprocessor. CoRR (2022)
Yugal Maheshwari, Kleber Stangherlin, Derek Wright, Manoj Sachdev
Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop. ICECS (2021)
Dhruv Patel, Adam Neale, Derek Wright, Manoj Sachdev
Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. 68 (8) (2021)
Kleber Hugo Stangherlin, Manoj Sachdev
Reliable Strong PUF Enrollment and Operation with Temperature and Voltage Optimization. ISQED (2021)
Qing Li, Czang-Ho Lee, Mohsen Asad, William S. Wong, Manoj Sachdev
Energy-Efficient Full-Swing Logic Circuits With Unipolar TFTs on Flexible Substrates. IEEE J. Solid State Circuits 56 (6) (2021)
Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev
Monitoring Aging Defects in STT-MRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Qing Li, Czang-Ho Lee, William S. Wong, Manoj Sachdev
Realization of an Energy-Efficient, Full-Swing Decoder with Unipolar TFT Technology. CICC (2020)
Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev
Accelerating STT-MRAM Ramp-up Characterization. NEWCAS (2020)
Ata Khorami, Roghayeh Saeidi, Manoj Sachdev
A low-power low-offset charge-sharing technique for double-tail comparators. Microelectron. J. 102 (2020)
Dhruv Patel, Adam Neale, Derek Wright, Manoj Sachdev
Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2019)
Zhuanhao Wu, Hiren D. Patel, Manoj Sachdev, Mahesh V. Tripunitara
Strengthening PUFs using Composition. ICCAD (2019)
Manoj Sachdev
Tutorial 2B: Offset Mitigation in Low-Voltage Sense Amplifiers and Its Implication on SRAM Design and Test. SoCC (2019)
Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev
A Parametric DFT Scheme for STT-MRAMs. IEEE Trans. Very Large Scale Integr. Syst. 27 (7) (2019)
Ata Khorami, Roghayeh Saeidi, Manoj Sachdev, Mohammad Sharifkhani
A low-power dynamic comparator for low-offset applications. Integr. 69 (2019)
Ata Khorami, Manoj Sachdev, Mohammad Sharifkhani
A Contention-free, Static, Single-phase Flip-Flop for Low Data Activity Applications. SoCC (2019)
Morteza Nabavi, Manoj Sachdev
A 290-mV, 3.34-MHz, 6T SRAM With pMOS Access Transistors and Boosted Wordline in 65-nm CMOS Technology. IEEE J. Solid State Circuits 53 (2) (2018)
Mahdi Elghazali, Manoj Sachdev, Ajoy Opal
An ESD transient clamp with 494 pA leakage current in GP 65 nm CMOS technology. ISQED (2018)
Dhruv Patel, Derek Wright, Manoj Sachdev
Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm. ETS (2018)
Mahdi Elghazali, Manoj Sachdev, Ajoy Opal
A Low-Leakage, Robust ESD Clamp with Thyristor Delay Element in 65 nm CMOS Technology. ISVLSI (2016)
Jaspal Singh Shah, Manoj Sachdev
Radiation hardened pulsed-latches in 65-nm CMOS. CCECE (2016)
Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev
Runtime slack-deficit detection for a low-voltage DCT circuit. MWSCAS (2015)
Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev
Voltage-Boosted Synchronizers. ACM Great Lakes Symposium on VLSI (2015)
Adam Neale, Maarten Jonkman, Manoj Sachdev
Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMs. IEEE Trans. Circuits Syst. II Express Briefs (4) (2015)
Adam Neale, Manoj Sachdev
A low energy SRAM-based physically unclonable function primitive in 28 nm CMOS. CICC (2015)
Afshin Seraj, Mohammad Maymandi-Nejad, Parvin Bahmanyar, Manoj Sachdev
A Linear Comparator-Based Fully Digital Delay Element. ISVLSI (2015)
Pierce I-Jen Chuang, Manoj Sachdev, Vincent C. Gaudet
VLSI implementation of high-throughput, low-energy, configurable MIMO detector. ICCD (2015)
Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev
An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only). FPGA (2015)
Tahseen Shakir, Manoj Sachdev
A body-bias based current sense amplifier for high-speed low-power embedded SRAMs. SoCC (2014)
Manoj Sachdev, Tetsuya Iizuka
Embedded tutorial: Test and manufacturability for silicon photonics and 3D integration. CICC (2014)
Mahdi Elghazali, Manoj Sachdev, Ajoy Opal
A low-leakage, hybrid ESD power supply clamp in 65nm CMOS technology. CICC (2014)
Adam Neale, Manoj Sachdev
A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC. CICC (2014)
Mahdi Elghazali, Manoj Sachdev, Ajoy Opal
A hybrid ESD clamp with thyristor delay element and diodes for low-leakage applications. NEWCAS (2014)
Pierce I-Jen Chuang, Manoj Sachdev, Vincent C. Gaudet
A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2014)
Tasreen Charania, Ajoy Opal, Manoj Sachdev
Analysis and Design of On-Chip Decoupling Capacitors. IEEE Trans. Very Large Scale Integr. Syst. 21 (4) (2013)
Jaspal Singh Shah, David Nairn, Manoj Sachdev
An Energy-Efficient Offset-Cancelling Sense Amplifier. IEEE Trans. Circuits Syst. II Express Briefs (8) (2013)
Pierce Chuang, David Li, Manoj Sachdev
Constant Delay Logic Style. IEEE Trans. Very Large Scale Integr. Syst. 21 (3) (2013)
Maofeng Yang, Nikolas P. Papadopoulos, Czang-Ho Lee, William S. Wong, Manoj Sachdev
A novel voltage-programmed pixel circuit with VT-shift compensation for AMOLED displays. CICC (2013)
David Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Richard Wong
Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2012)
Pierce Chuang, David Li, Manoj Sachdev, Vincent C. Gaudet
A 148ps 135mW 64-bit adder with Constant-Delay logic in 65nm CMOS. CICC (2012)
Tahseen Shakir, Manoj Sachdev
A word-line boost driver design for low operating voltage 6T-SRAMs. MWSCAS (2012)
Jaspal Singh Shah, David Nairn, Manoj Sachdev
A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm. VLSI-SoC (2012)
Mike Li, Manoj Sachdev
Power delivery: Droop, jitter, test and debug story (Tutorial). CICC (2012)
Pierce Chuang, David Li, Manoj Sachdev
A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator. IEEE Trans. Circuits Syst. II Express Briefs (2) (2012)
Tahseen Shakir, Manoj Sachdev
A read-assist write-back voltage sense amplifier for low voltage-operated SRAMs. SoCC (2012)
Tasreen Charania, Pierce Chuang, Ajoy Opal, Manoj Sachdev
Suppression of on-chip power supply noise generated by a 64-bit static logic ALU block. VLSI-SoC (2012)
David Li, David Rennie, Pierce Chuang, David Nairn, Manoj Sachdev
Design and analysis of metastable-hardened and soft-error tolerant high-performance, low-power flip-flops. ISQED (2011)
David Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Rick Wong
Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS. CICC (2011)
Tasreen Charania, Pierce Chuang, Ajoy Opal, Manoj Sachdev
Analysis of power supply noise mitigation circuits. CCECE (2011)
Muhammad Nummer, Manoj Sachdev
Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths. J. Electron. Test. 27 (1) (2011)
David Li, Pierce Chuang, David Nairn, Manoj Sachdev
Design and analysis of metastable-hardened flip-flops in sub-threshold region. ISLPED (2011)
Danny Teng-Hsiang Tsuei, Mohamed-Yahia Dabbagh, Manoj Sachdev
Multiprocessor FPGA implementation of a 2D digital filter. CCECE (2011)
Mohammad Sharifkhani, E. Rahiminejad, Shah M. Jahinuzzaman, Manoj Sachdev
A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 19 (5) (2011)
Adam Neale, Manoj Sachdev
Digitally programmable SRAM timing for nano-scale technologies. ISQED (2011)
David Li, Pierce Chuang, Manoj Sachdev
Comparative analysis and study of metastability on high-performance flip-flops. ISQED (2010)
Manoj Sachdev, Hong-Ha Vuong
ESD design challenges. CICC (2009)
Nitin Mohan, Manoj Sachdev
Low-Leakage Storage Cells for Ternary Content Addressable Memories. IEEE Trans. Very Large Scale Integr. Syst. 17 (5) (2009)
Mohammad Sharifkhani, Manoj Sachdev
SRAM Cell Stability: A Dynamic Perspective. IEEE J. Solid State Circuits 44 (2) (2009)
Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev
An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 17 (9) (2009)
Shah M. Jahinuzzaman, Jaspal Singh Shah, David J. Rennie, Manoj Sachdev
Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC. IEEE J. Solid State Circuits 44 (9) (2009)
Nitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev
A Low-Power Ternary CAM With Positive-Feedback Match-Line Sense Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2009)
Pierce Chuang, David Li, Manoj Sachdev
Design of a 64-bit Low-energy High-performance Adder using Dynamic Feedthrough Logic. ISCAS (2009)
Hossein Sarbishaei, Manoj Sachdev
ESD protection circuit for 8.5Gbps I/Os in 90nm CMOS technology. CICC (2009)
Mohammad Sharifkhani, Manoj Sachdev
An Energy Efficient 40 Kb SRAM Module With Extended Read/Write Noise Margin in 0.13 µm CMOS. IEEE J. Solid State Circuits 44 (2) (2009)
Shah M. Jahinuzzaman, Tahseen Shakir, Sumanjit Lubana, Jaspal Singh Shah, Manoj Sachdev
A multiword based high speed ECC scheme for low-voltage embedded SRAMS. ESSCIRC (2008)
Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev
Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model. ISQED (2008)
Hooman Farkhani, Mohammad Maymandi-Nejad, Manoj Sachdev
A fully digital ADC using a new delay element with enhanced linearity. ISCAS (2008)
David Rennie, Manoj Sachdev
A 5-Gb/s CDR Circuit With Automatically Calibrated Linear Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2008)
David Rennie, Manoj Sachdev
A Novel Tri-State Binary Phase Detector. ISCAS (2007)
Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev
Dynamic Data Stability in Low-power SRAM Design. CICC (2007)
Mohamed Elgebaly, Manoj Sachdev
Variation-Aware Adaptive Voltage Scaling System. IEEE Trans. Very Large Scale Integr. Syst. 15 (5) (2007)
David Rennie, Manoj Sachdev
Comparative Robustness of CML Phase Detectors for Clock and Data Recovery Circuits. ISQED (2007)
Mohammad Sharifkhani, Manoj Sachdev
Segmented Virtual Ground Architecture for Low-Power Embedded SRAM. IEEE Trans. Very Large Scale Integr. Syst. 15 (2) (2007)
Nitin Mohan, Manoj Sachdev
Low-Capacitance and Charge-Shared Match Lines for Low-Energy High-Performance TCAMs. IEEE J. Solid State Circuits 42 (9) (2007)
Hossein Sarbishaei, Oleg Semenov, Manoj Sachdev
Optimizing Circuit Performance and ESD Protection for High-Speed Differential I/Os. CICC (2007)
Nitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev
Match Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable Memories. CICC (2006)
Bashir M. Al-Hashimi, Dimitris Gizopoulos, Manoj Sachdev, Adit D. Singh
New JETTA Editors, 2006. J. Electron. Test. 22 (1) (2006)
Oleg Semenov, Hossein Sarbishaei, Valery Axelrad, Manoj Sachdev
Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices. Microelectron. J. 37 (6) (2006)
Nitin Mohan, Manoj Sachdev
Novel Ternary Storage Cells and Techniques for Leakage Reduction in Ternary CAM. SoCC (2006)
Nitin Mohan, Wilson Fung, Manoj Sachdev
Low-Power Priority Encoder and Multiple Match Detection Circuit for Ternary Content Addressable Memory. SoCC (2006)
Nitin Mohan, Wilson Fung, Derek Wright, Manoj Sachdev
Design techniques and test methodology for low-power TCAMs. IEEE Trans. Very Large Scale Integr. Syst. 14 (6) (2006)
Mohammad Sharifkhani, Manoj Sachdev
A low power SRAM architecture based on segmented virtual grounding. ISLPED (2006)
Mohammad Sharifkhani, Manoj Sachdev
-Order ΔΣ Frequency Digitizer. CICC (2006)
Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez
Weak Cell Detection in Deep-Submicron SRAMs: A Programmable Detection Technique. IEEE J. Solid State Circuits 41 (10) (2006)
Mohammad Sharifkhani, Manoj Sachdev
A phase-domain 2nd-order continuous time Delta-Sigma-modulator for frequency digitization. ISCAS (2006)
Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev
Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests. MTDT (2006)
Mohammad Maymandi-Nejad, Manoj Sachdev
DTMOS Technique for Low-Voltage Analog Circuits. IEEE Trans. Very Large Scale Integr. Syst. 14 (10) (2006)
Mohammad Maymandi-Nejad, Manoj Sachdev
A 0.8V Delta-Sigma modulator using DTMOS technique. ISCAS (4) (2005)
Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies. Microelectron. J. 36 (9) (2005)
Andrei Pavlov, Manoj Sachdev, José Pineda de Gyvez, Mohamed Azimane
Programmable techniques for cell stability test and debug in embedded SRAMs. CICC (2005)
Oleg Semenov, Hossein Sarbishaei, Manoj Sachdev
Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment. ISQED (2005)
Bhaskar Chatterjee, Manoj Sachdev
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology. IEEE Trans. Very Large Scale Integr. Syst. 13 (11) (2005)
Mohammad Maymandi-Nejad, Manoj Sachdev
A monotonic digitally controlled delay element. IEEE J. Solid State Circuits 40 (11) (2005)
Andrei Pavlov, Mohamed Azimane, José Pineda de Gyvez, Manoj Sachdev
Word line pulsing technique for stability fault detection in SRAM cells. ITC (2005)

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Publication Activity (10 Years)

Top Topics

Top Venues

Manoj Sachdev