An ESD transient clamp with 494 pA leakage current in GP 65 nm CMOS technology.

Mahdi Elghazali Manoj Sachdev Ajoy Opal

Published in: ISQED (2018)

Keyphrases

leakage current
low voltage
cmos technology
low power
power consumption
power line
spl times
parallel processing
design considerations
power dissipation
high speed
image sensor
low cost
random access memory
power management
silicon on insulator