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Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS.
David Rennie
David Li
Manoj Sachdev
Bharat L. Bhuva
Srikanth Jagannathan
Shi-Jie Wen
Richard Wong
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2012)
Keyphrases
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flip flops
trade off
cmos technology
low power
power dissipation
multiple input
nm technology
high speed
power consumption
low cost
neural network
image processing
case study
input output
efficient implementation
digital signal processing