Bharat L. Bhuva

Publication Activity (10 Years)

Years Active: 1989-2024
Publications (10 Years): 27

Top Topics

Comparative Study

Semiconductor Devices

Top Venues

J. Electron. Test.

Microelectron. J.

Publications

Jenna B. Kronenberg, Yoni Xiong, Nicholas J. Pieper, Dennis R. Ball, Bharat L. Bhuva
Single-Event Performance of Flip Flop Designs at the 5-nm Bulk FinFET Node at Near-Threshold Supply Voltages. IRPS (2024)
Balaji Narasimham, A-R. Montoya, C. Paone, T. Riehle, Mike Smith, Liming Tsau, Dennis R. Ball, Bharat L. Bhuva
Scaling Trends and Bias Dependence of SRAM SER from 16-nm to 3-nm FinFET. IRPS (2024)
Yoni Xiong, Nicholas J. Pieper, Jenna B. Kronenberg, Dennis R. Ball, Megan Casey, Bharat L. Bhuva
Multiple Bit Upsets in Register Circuits at the 5-nm Bulk FinFET Node. IRPS (2024)
Nicholas J. Pieper, M. Chun, Yoni Xiong, H. M. Dattilo, Jenna B. Kronenberg, Sanghyeon Baeg, Shi-Jie Wen, Rita Fung, D. Chan, C. Escobar, Bharat L. Bhuva
Total-Ionizing Dose Damage from X-Ray PCB Inspection Systems. IRPS (2024)
Yoni Xiong, Yueh Chiang, Nicholas J. Pieper, Dennis R. Ball, Bharat L. Bhuva
Soft Error Rate Predictions for Terrestrial Neutrons at the 3-nm Bulk FinFET Technology. IRPS (2023)
N. J. Pieper, Yoni Xiong, Dennis R. Ball, J. Pasternak, Bharat L. Bhuva
Effects of Collected Charge and Drain Area on SE Response of SRAMs at the 5-nm FinFET Node. IRPS (2023)
N. J. Pieper, Yoni Xiong, Alexandra Feeley, Dennis R. Ball, Bharat L. Bhuva
Single-Event Latchup Vulnerability at the 7-nm FinFET Node. IRPS (2022)
Yoni Xiong, Alexandra Feeley, N. J. Pieper, Dennis R. Ball, Balaji Narasimham, John Brockman, N. A. Dodds, S. A. Wender, Shi-Jie Wen, Rita Fung, Bharat L. Bhuva
Soft Error Characterization of D-FFs at the 5-nm Bulk FinFET Technology for the Terrestrial Environment. IRPS (2022)
Yoni Xiong, Alexandra Feeley, Lloyd W. Massengill, Bharat L. Bhuva, Shi-Jie Wen, Rita Fung
Frequency, LET, and Supply Voltage Dependence of Logic Soft Errors at the 7-nm Node. IRPS (2021)
Alexandra Feeley, Yoni Xiong, Bharat L. Bhuva, Balaji Narasimham, Shi-Ji Wen, Rita Fung
Effects of Temperature and Supply Voltage on Soft Errors for 7-nm Bulk FinFET Technology. IRPS (2021)
Balaji Narasimham, Vikas Chaudhary, Mike Smith, Liming Tsau, Dennis Ball, Bharat L. Bhuva
Scaling Trends in the Soft Error Rate of SRAMs from Planar to 5-nm FinFET. IRPS (2021)
Lyuan Xu, Jingchen Cao, John Brockman, Carlo Cazzaniga, Christopher Frost, Shi-Jie Wen, Rita Fung, Bharat L. Bhuva
Thermal Neutron Induced Soft Errors in 7-nm Bulk FinFET Node. IRPS (2020)
Jingchen Cao, Lyuan Xu, Shi-Jie Wen, Rita Fung, Balaji Narasimham, Lloyd W. Massengill, Bharat L. Bhuva
Temperature Dependence of Single-Event Transient Pulse Widths for 7-nm Bulk FinFET Technology. IRPS (2020)
Lyuan Xu, Jingchen Cao, Shi-Jie Wen, Rita Fung, Jamie Markevitch, Dennis R. Ball, Bharat L. Bhuva
High-Current State triggered by Operating-Frequency Change. IRPS (2020)
J. Cao, L. Xu, Bharat L. Bhuva, S.-J. Wen, R. Wong, Balaji Narasimham, Lloyd W. Massengill
Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET Technologies. IRPS (2019)
L. Xu, J. Cao, Bharat L. Bhuva, Indranil Chatterjee, S.-J. Wen, R. Wong, Lloyd W. Massengill
Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology. IRPS (2019)
Balaji Narasimham, K. Chandrasekharan, J. K. Wang, Bharat L. Bhuva
Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes. IRPS (2019)
S. A. Wender, J. M. O'Donnell, L. Zavorka, Bharat L. Bhuva
Neutron Beam Attenuation Through Semiconductor Devices During SEU Testing. IRPS (2019)
H. Zhang, H. Jiang, M. R. Eaker, K. J. Lezon, Balaji Narasimham, Nihaar N. Mahatme, Lloyd W. Massengill, Bharat L. Bhuva
Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology. IRPS (2018)
Hui Jiang, H. Zhang, R. C. Harrington, J. A. Maharrey, J. S. Kauppila, Lloyd W. Massengill, Bharat L. Bhuva
Impact of supply voltage and particle LET on the soft error rate of logic circuits. IRPS (2018)
K. J. Lezon, S.-J. Wen, Y.-F. Dan, R. Wong, Bharat L. Bhuva
Single-event effects on optical transceiver. IRPS (2018)
H. Jiang, H. Zhang, Balaji Narasimham, Lloyd W. Massengill, Bharat L. Bhuva
Designing soft-error-aware circuits with power and speed optimization. IRPS (2018)
Alexandre Simionovski, Gilson I. Wirth, Ronald D. Schrimpf, Bharat L. Bhuva
A TCAD evaluation of a single Bulk-BICS with integrative memory cell. Microelectron. J. 80 (2018)
R. M. Chen, E. X. Zhang, Bharat L. Bhuva
Single-event performance of differential flip-flop designs and hardening implication. IOLTS (2016)
Nihaar N. Mahatme, Bharat L. Bhuva, Nelson J. Gaspard, T. Assis, Y. Xu, P. Marcoux, M. Vilchis, Balaji Narasimham, A. Shih, Shi-Jie Wen, Rick Wong, N. Tam, M. Shroff, S. Koyoma, A. Oates
Terrestrial SER characterization for nanoscale technologies: A comparative study. IRPS (2015)
N. Tam, Bharat L. Bhuva, Lloyd W. Massengill, D. Ball, Michael W. McCurdy, Michael L. Alles, Indranil Chatterjee
Multi-cell soft errors at the 16-nm FinFET technology node. IRPS (2015)
Balaji Narasimham, Jung K. Wang, Narayana Vedula, Saket Gupta, Brandon Bartz, Carl Monzel, Indranil Chatterjee, Bharat L. Bhuva, Ronald D. Schrimpf, Robert A. Reed
Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs. IRPS (2015)
Yi Ren, Anlin He, Shuting Shi, Gang Guo, Li Chen, Shi-Jie Wen, Richard Wong, N. W. van Vonno, Bharat L. Bhuva
Single-Event Transient Measurements on a DC/DC Pulse Width Modulator Using Heavy Ion, Proton, and Pulsed Laser. J. Electron. Test. 30 (1) (2014)
Zhichao Zhang, Yi Ren, Li Chen, Nelson J. Gaspard, Arthur F. Witulski, W. Timothy Holman, Bharat L. Bhuva, Shi-Jie Wen, Ramaswami Sammynaiken
A Bulk Built-In Voltage Sensor to Detect Physical Location of Single-Event Transients. J. Electron. Test. 29 (2) (2013)
Nihaar N. Mahatme, Indranil Chatterjee, Akash Patki, Daniel B. Limbrick, Bharat L. Bhuva, Ronald D. Schrimpf, William H. Robinson
An efficient technique to select logic nodes for single event transient pulse-width reduction. Microelectron. Reliab. 53 (1) (2013)
Yi Ren, L. Fan, Li Chen, Shi-Jie Wen, Richard Wong, N. W. van Vonno, Arthur F. Witulski, Bharat L. Bhuva
Single-Event Effects Analysis of a Pulse Width Modulator IC in a DC/DC Converter. J. Electron. Test. 28 (6) (2012)
David Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Richard Wong
Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2012)
David Rennie, David Li, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, Shi-Jie Wen, Rick Wong
Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS. CICC (2011)
Daniel B. Limbrick, Suge Yue, William H. Robinson, Bharat L. Bhuva
Impact of Synthesis Constraints on Error Propagation Probability of Digital Circuits. DFT (2011)
Patrick R. Fleming, Brian D. Olson, W. Timothy Holman, Bharat L. Bhuva, Lloyd W. Massengill
Design Technique for Mitigation of Soft Errors in Differential Switched-Capacitor Circuits. IEEE Trans. Circuits Syst. II Express Briefs (9) (2008)
Venkata S. Rangavajjhala, Bharat L. Bhuva, Sherra E. Kerns
Statistical degradation analysis of digital CMOS IC's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (6) (1993)
Neeraj Kaul, Gautam Biswas, Bharat L. Bhuva
Multi-level qualitative reasoning applied to CMOS digital circuits. Artif. Intell. Eng. 7 (3) (1992)
Bharat L. Bhuva, John J. Paulos, Ronald S. Gyurcsik, Sherra E. Kerns
Switch-level simulation of total dose effects on CMOS VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 (9) (1989)