Balaji Narasimham

Publication Activity (10 Years)

Years Active: 2015-2024
Publications (10 Years): 14

Top Topics

Gigabit Ethernet

Cmos Technology

Top Venues

Publications

Balaji Narasimham, A-R. Montoya, C. Paone, T. Riehle, Mike Smith, Liming Tsau, Dennis R. Ball, Bharat L. Bhuva
Scaling Trends and Bias Dependence of SRAM SER from 16-nm to 3-nm FinFET. IRPS (2024)
Balaji Narasimham, H. Luk, C. Paone, A-R. Montoya, T. Riehle, Mike Smith, Liming Tsau
Scaling Trends and the Effect of Process Variations on the Soft Error Rate of advanced FinFET SRAMs. IRPS (2023)
Yoni Xiong, Alexandra Feeley, N. J. Pieper, Dennis R. Ball, Balaji Narasimham, John Brockman, N. A. Dodds, S. A. Wender, Shi-Jie Wen, Rita Fung, Bharat L. Bhuva
Soft Error Characterization of D-FFs at the 5-nm Bulk FinFET Technology for the Terrestrial Environment. IRPS (2022)
Alexandra Feeley, Yoni Xiong, Bharat L. Bhuva, Balaji Narasimham, Shi-Ji Wen, Rita Fung
Effects of Temperature and Supply Voltage on Soft Errors for 7-nm Bulk FinFET Technology. IRPS (2021)
Balaji Narasimham, Vikas Chaudhary, Mike Smith, Liming Tsau, Dennis Ball, Bharat L. Bhuva
Scaling Trends in the Soft Error Rate of SRAMs from Planar to 5-nm FinFET. IRPS (2021)
Jingchen Cao, Lyuan Xu, Shi-Jie Wen, Rita Fung, Balaji Narasimham, Lloyd W. Massengill, Bharat L. Bhuva
Temperature Dependence of Single-Event Transient Pulse Widths for 7-nm Bulk FinFET Technology. IRPS (2020)
J. Cao, L. Xu, Bharat L. Bhuva, S.-J. Wen, R. Wong, Balaji Narasimham, Lloyd W. Massengill
Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET Technologies. IRPS (2019)
Balaji Narasimham, K. Chandrasekharan, J. K. Wang, Bharat L. Bhuva
Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes. IRPS (2019)
H. Zhang, H. Jiang, M. R. Eaker, K. J. Lezon, Balaji Narasimham, Nihaar N. Mahatme, Lloyd W. Massengill, Bharat L. Bhuva
Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology. IRPS (2018)
H. Jiang, H. Zhang, Balaji Narasimham, Lloyd W. Massengill, Bharat L. Bhuva
Designing soft-error-aware circuits with power and speed optimization. IRPS (2018)
Balaji Narasimham, Saket Gupta, Daniel S. Reed, J. K. Wang, Nick Hendrickson, Hasan Taufique
Scaling trends and bias dependence of the soft error rate of 16 nm and 7 nm FinFET SRAMs. IRPS (2018)
Balaji Narasimham, Tim Wu, Jung K. Wang, Bruce Conway
Evaluation of the system-level SER performance of gigabit ethernet transceiver devices. IRPS (2018)
Nihaar N. Mahatme, Bharat L. Bhuva, Nelson J. Gaspard, T. Assis, Y. Xu, P. Marcoux, M. Vilchis, Balaji Narasimham, A. Shih, Shi-Jie Wen, Rick Wong, N. Tam, M. Shroff, S. Koyoma, A. Oates
Terrestrial SER characterization for nanoscale technologies: A comparative study. IRPS (2015)
Balaji Narasimham, Jung K. Wang, Narayana Vedula, Saket Gupta, Brandon Bartz, Carl Monzel, Indranil Chatterjee, Bharat L. Bhuva, Ronald D. Schrimpf, Robert A. Reed
Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs. IRPS (2015)