Saket Gupta

Publication Activity (10 Years)

Years Active: 2010-2024
Publications (10 Years): 4

Top Topics

Optimal Location

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

J. Supercomput.

Publications

Udit Mittal, Uma Nangia, Narender Kumar Jain, Saket Gupta
Optimal power flow solution using a learning-based sine-cosine algorithm. J. Supercomput. 80 (11) (2024)
Sandeep Sharma, Saket Gupta, Mohd Zuhaib, Vijay Bhuria, Hasmat Malik, Abdulaziz Almutairi, Asyraf Afthanorhan, Mohammad Asef Hossaini
A Comprehensive Review on STATCOM: Paradigm of Modeling, Control, Stability, Optimal Location, Integration, Application, and Installation. IEEE Access 12 (2024)
Balaji Narasimham, Saket Gupta, Daniel S. Reed, J. K. Wang, Nick Hendrickson, Hasan Taufique
Scaling trends and bias dependence of the soft error rate of 16 nm and 7 nm FinFET SRAMs. IRPS (2018)
Saket Gupta, Carl Monzel, Daniel S. Reed, Yifei Zhang, Mark Winter, Myron Buer
Bitcell-Based Design of On-Chip Process Variability Monitors for Sub-28 nm Memories. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2016)
Balaji Narasimham, Jung K. Wang, Narayana Vedula, Saket Gupta, Brandon Bartz, Carl Monzel, Indranil Chatterjee, Bharat L. Bhuva, Ronald D. Schrimpf, Robert A. Reed
Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs. IRPS (2015)
Saket Gupta, Sachin S. Sapatnekar
Variation-Aware Variable Latency Design. IEEE Trans. Very Large Scale Integr. Syst. 22 (5) (2014)
Sparsh Mittal, Saket Gupta, Ankush Mittal
BioinQA: metadata-based multi-document QA system for addressing the issues in biomedical domain. Int. J. Data Min. Model. Manag. 5 (1) (2013)
Saket Gupta, Sachin S. Sapatnekar
Employing circadian rhythms to enhance power and reliability. ACM Trans. Design Autom. Electr. Syst. 18 (3) (2013)
Ayan Paul, Matt Amrein, Saket Gupta, Arvind Vinod, Abhishek Arun, Sachin S. Sapatnekar, Chris H. Kim
Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors. CICC (2012)
Saket Gupta, Sachin S. Sapatnekar
BTI-aware design using variable latency units. ASP-DAC (2012)
Saket Gupta, Sachin S. Sapatnekar
Compact Current Source Models for Timing Analysis Under Temperature and Body Bias Variations. IEEE Trans. Very Large Scale Integr. Syst. 20 (11) (2012)
Jianxin Fang, Saket Gupta, Sanjay V. Kumar, Sravan K. Marella, Vivek Mishra, Pingqiang Zhou, Sachin S. Sapatnekar
Circuit reliability: From Physics to Architectures: Embedded tutorial paper. ICCAD (2012)
Saket Gupta, Sachin S. Sapatnekar
GNOMO: Greater-than-NOMinal Vdd operation for BTI mitigation. ASP-DAC (2012)
Saket Gupta, Sachin S. Sapatnekar
Current source modeling in the presence of body bias. ASP-DAC (2010)