Sanjay V. Kumar

Publication Activity (10 Years)

Years Active: 2006-2012
Publications (10 Years): 0

Top Topics

Evolvable Hardware

Real Time Embedded

Reliability Analysis

Top Venues

Publications

Sravan K. Marella, Sanjay V. Kumar, Sachin S. Sapatnekar
A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations. ICCAD (2012)
Jianxin Fang, Saket Gupta, Sanjay V. Kumar, Sravan K. Marella, Vivek Mishra, Pingqiang Zhou, Sachin S. Sapatnekar
Circuit reliability: From Physics to Architectures: Embedded tutorial paper. ICCAD (2012)
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
Adaptive Techniques for Overcoming Performance Degradation Due to Aging in CMOS Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19 (4) (2011)
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
Adaptive techniques for overcoming performance degradation due to aging in digital circuits. ASP-DAC (2009)
Yong Zhan, Sanjay V. Kumar, Sachin S. Sapatnekar
Thermally Aware Design. Found. Trends Electron. Des. Autom. 2 (3) (2008)
Sanjay V. Kumar, Chandramouli V. Kashyap, Sachin S. Sapatnekar
A framework for block-based timing sensitivity analysis. DAC (2008)
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
Body Bias Voltage Computations for Process and Temperature Compensation. IEEE Trans. Very Large Scale Integr. Syst. 16 (3) (2008)
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
NBTI-Aware Synthesis of Digital Circuits. DAC (2007)
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
An analytical model for negative bias temperature instability. ICCAD (2006)
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
Impact of NBTI on SRAM Read Stability and Design for Reliability. ISQED (2006)
Sanjay V. Kumar, Chris H. Kim, Sachin S. Sapatnekar
Mathematically assisted adaptive body bias (ABB) for temperature compensation in gigascale LSI systems. ASP-DAC (2006)