K. Chandrasekharan

Publication Activity (10 Years)

Years Active: 2008-2019
Publications (10 Years): 1

Top Topics

Power Reduction

Cmos Technology

Top Venues

Publications

Balaji Narasimham, K. Chandrasekharan, J. K. Wang, Bharat L. Bhuva
Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes. IRPS (2019)
Gregory Uhlmann, Tony Aipperspach, Toshiaki Kirihata, K. Chandrasekharan, Yan Zun Li, Chris Paone, Brian Reed, Norman Robson, John Safran, David Schmitt, Subramanian S. Iyer
A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS. ISSCC (2008)