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Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes.
Balaji Narasimham
K. Chandrasekharan
J. K. Wang
Bharat L. Bhuva
Published in:
IRPS (2019)
Keyphrases
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high speed
low power
cmos technology
power reduction
design process
power consumption
computer aided
design space
databases
design methodology
search engine
case study
error bounds