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Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology.
L. Xu
J. Cao
Bharat L. Bhuva
Indranil Chatterjee
S.-J. Wen
R. Wong
Lloyd W. Massengill
Published in:
IRPS (2019)
Keyphrases
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flip flops
cmos technology
nm technology
silicon on insulator
case study
computer systems
event detection
computer vision
pattern recognition
low power
image formation
power dissipation