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Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS.

David RennieDavid LiManoj SachdevBharat L. BhuvaSrikanth JagannathanShi-Jie WenRick Wong
Published in: CICC (2011)
Keyphrases
  • flip flops
  • cmos technology
  • power dissipation
  • low power
  • silicon on insulator
  • low cost
  • power consumption
  • low voltage
  • nm technology
  • high speed
  • computer vision
  • case study
  • pattern recognition
  • digital signal processing