A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm.

Jaspal Singh Shah David Nairn Manoj Sachdev

Published in: VLSI-SoC (2012)

Keyphrases

leakage current
knowledge base
low power
access control
estimation error
database
real time
video sequences
error bounds
partial occlusion
data transmission