Bhaskar Chatterjee

Publication Activity (10 Years)

Years Active: 2002-2005
Publications (10 Years): 0

Publications

Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies. Microelectron. J. 36 (9) (2005)
Bhaskar Chatterjee, Manoj Sachdev
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology. IEEE Trans. Very Large Scale Integr. Syst. 13 (11) (2005)
Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
DFT for Delay Fault Testing of High-Performance Digital Circuits. IEEE Des. Test Comput. 21 (3) (2004)
Christine Kwong, Bhaskar Chatterjee, Manoj Sachdev
Modeling and designing energy-delay optimized wide domino circuits. ISCAS (2) (2004)
Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies. ISQED (2004)
Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies. ISLPED (2004)
Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs. ITC (2004)
Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. ISLPED (2003)
Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
A DFT Technique for Low Frequency Delay Fault Testing in High Performance Digital Circuits. ITC (2002)