Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology.
Bhaskar ChatterjeeManoj SachdevPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2005)
Keyphrases
- cmos technology
- low power
- power dissipation
- power consumption
- high speed
- low cost
- single chip
- low voltage
- nm technology
- logic circuits
- mixed signal
- low power consumption
- power reduction
- vlsi architecture
- gate array
- clock frequency
- digital signal processing
- parallel processing
- image sensor
- energy efficiency
- power management
- energy saving
- design methodology
- signal processing
- high resolution
- floating point
- efficient implementation