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A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS.
Pierce I-Jen Chuang
Manoj Sachdev
Vincent C. Gaudet
Published in:
IEEE Trans. Circuits Syst. I Regul. Pap. (2014)
Keyphrases
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binary tree
random access memory
power consumption
quadtree
delay insensitive
power supply
hierarchical structure
multiclass svm
nm technology
hd video
computer vision
tree representation
data structure
design considerations
low power
predictive coding
low voltage
modal logic
multiresolution