Shah M. Jahinuzzaman

Publication Activity (10 Years)

Years Active: 2006-2015
Publications (10 Years): 1

Top Topics

Power Reduction

Dynamic Random Access Memory

Associative Memory

Top Venues

Publications

Norbert Seifert, Shah M. Jahinuzzaman, Jyothi Velamala, Nikunj Patel
Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets. IRPS (2015)
Wasim Hussain, Shah M. Jahinuzzaman
A read-decoupled gated-ground SRAM architecture for low-power embedded memories. Integr. 45 (3) (2012)
Wasim Hussain, Shah M. Jahinuzzaman
A 7T SRAM bit-cell for low-power embedded memories. ACM Great Lakes Symposium on VLSI (2011)
Mohammad Sharifkhani, E. Rahiminejad, Shah M. Jahinuzzaman, Manoj Sachdev
A Compact Hybrid Current/Voltage Sense Amplifier With Offset Cancellation for High-Speed SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 19 (5) (2011)
Hourieh Attarzadeh, Mohammad Sharifkhani, Shah M. Jahinuzzaman
A scalable offset-cancelled current/voltage sense amplifier. ISCAS (2010)
Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev
An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs. IEEE Trans. Very Large Scale Integr. Syst. 17 (9) (2009)
Shah M. Jahinuzzaman, Jaspal Singh Shah, David J. Rennie, Manoj Sachdev
Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC. IEEE J. Solid State Circuits 44 (9) (2009)
Shah M. Jahinuzzaman, Tahseen Shakir, Sumanjit Lubana, Jaspal Singh Shah, Manoj Sachdev
A multiword based high speed ECC scheme for low-voltage embedded SRAMS. ESSCIRC (2008)
Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev
Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model. ISQED (2008)
Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev
Dynamic Data Stability in Low-power SRAM Design. CICC (2007)
Mohammad Sharifkhani, Shah M. Jahinuzzaman, Manoj Sachdev
Dynamic Data Stability in SRAM Cells and Its Implications on Data Stability Tests. MTDT (2006)