A Low-Leakage, Robust ESD Clamp with Thyristor Delay Element in 65 nm CMOS Technology.

Mahdi Elghazali Manoj Sachdev Ajoy Opal

Published in: ISVLSI (2016)

Keyphrases

cmos technology
power dissipation
low power
power consumption
low voltage
parallel processing
high speed
spl times
silicon on insulator
real time