A 0.4 V 75 kbit SRAM macro in 28 nm CMOS featuring a 3-adjacent MBU correcting ECC.
Adam NealeManoj SachdevPublished in: CICC (2014)
Keyphrases
- cmos technology
- power consumption
- nm technology
- low power
- random access memory
- low voltage
- leakage current
- silicon on insulator
- dynamic random access memory
- parallel processing
- chip design
- high speed
- power reduction
- error correction
- speaker dependent
- power dissipation
- error correcting
- power management
- metal oxide semiconductor
- low cost
- embedded dram
- vlsi circuits
- elliptic curve
- security analysis
- power supply
- elliptic curve cryptography
- image sensor
- design considerations
- real time
- digital signal processing
- speech recognition