Andrew A. Kennings

Publication Activity (10 Years)

Years Active: 1999-2020
Publications (10 Years): 16

Top Topics

Power Management

Miller Tucker Zemlin

Fpga Implementation

Top Venues

ACM Trans. Design Autom. Electr. Syst.

Publications

Aysa Fakheri Tabrizi, Nima Karimpour Darav, Logan Rakai, Ismail Bustany, Andrew A. Kennings, Laleh Behjat
Eh?Predictor: A Deep Learning Framework to Identify Detailed Routing Short Violations From a Placed Netlist. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (6) (2020)
Nima Karimpour Darav, Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu
Multi-Commodity Flow-Based Spreading in a Commercial Analytic Placer. FPGA (2019)
Aysa Fakheri Tabrizi, Nima Karimpour Darav, Shuchang Xu, Logan Rakai, Ismail Bustany, Andrew A. Kennings, Laleh Behjat
A machine learning framework to identify detailed routing short violations from a placed netlist. DAC (2018)
Andrew A. Kennings
Simple FPGA routing graph compression. CoRR (2018)
Nima Karimpour Darav, Ismail S. Bustany, Andrew A. Kennings, David T. Westwick, Laleh Behjat
Eh?Legalizer: A High Performance Standard-Cell Legalizer Observing Technology Constraints. ACM Trans. Design Autom. Electr. Syst. 23 (4) (2018)
Nima Karimpour Darav, Ismail S. Bustany, Andrew A. Kennings, Laleh Behjat
A Fast, Robust Network Flow-based Standard-Cell Legalization Method for Minimizing Maximum Movement. ISPD (2017)
Aysa Fakheri Tabrizi, Nima Karimpour Darav, Logan Rakai, Andrew A. Kennings, Laleh Behjat
Detailed routing violation prediction during placement using machine learning. VLSI-DAT (2017)
Nima Karimpour Darav, Ismail S. Bustany, Andrew A. Kennings, Ravi Mamidi
ICCAD-2017 CAD contest in multi-deck standard cell legalization and benchmarks. ICCAD (2017)
Nima Karimpour Darav, Andrew A. Kennings, Aysa Fakheri Tabrizi, David T. Westwick, Laleh Behjat
Eh?Placer: A High-Performance Modern Technology-Driven Placer. ACM Trans. Design Autom. Electr. Syst. 21 (3) (2016)
Jucemar Monteiro, Nima Karimpour Darav, Guilherme Flach, Mateus Fogaça, Ricardo Augusto da Luz Reis, Andrew A. Kennings, Marcelo O. Johann, Laleh Behjat
Routing-Aware Incremental Timing-Driven Placement. ISVLSI (2016)
Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev
Runtime slack-deficit detection for a low-voltage DCT circuit. MWSCAS (2015)
Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev
Voltage-Boosted Synchronizers. ACM Great Lakes Symposium on VLSI (2015)
Nima Karimpour Darav, Andrew A. Kennings, David T. Westwick, Laleh Behjat
High Performance Global Placement and Legalization Accounting for Fence Regions. ICCAD (2015)
Aysa Fakheri Tabrizi, Nima Karimpour Darav, Logan M. Rakai, Andrew A. Kennings, William Swartz, Laleh Behjat
A Detailed Routing-Aware Detailed Placement Technique. ISVLSI (2015)
Nima Karimpour Darav, Amin Farshidi, Aysa Fakheri Tabrizi, Emily Marasco, Amir Karbalaei, Andrew A. Kennings, Ismail S. Bustany, Laleh Behjat
The impact of industry-organized contests on EDA education. MSE (2015)
Yaoqiang Li, Pierce I-Jen Chuang, Andrew A. Kennings, Manoj Sachdev
An FPGA Implementation of a Timing-Error Tolerant Discrete Cosine Transform (Abstract Only). FPGA (2015)
Andrew A. Kennings, Nima Karimpour Darav, Laleh Behjat
Detailed placement accounting for technology constraints. VLSI-SoC (2014)
Sundaram Ananthanarayanan, Chirag Ravishankar, Siddharth Garg, Andrew A. Kennings
EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only). FPGA (2012)
Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings
Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms. ISQED (2012)
Chirag Ravishankar, Jason Helge Anderson, Andrew A. Kennings
FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (9) (2012)
Chirag Ravishankar, Andrew A. Kennings, Jason Helge Anderson
FPGA power reduction by guarded evaluation considering physical information. VLSI-SoC (2012)
Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings
EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip. FPL (2012)
Andrew A. Kennings, Chirag Ravishankar
Parallel FPGA technology mapping using multi-core architectures. CCECE (2011)
Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox
FPGA technology mapping with encoded libraries and staged priority cuts. ACM Trans. Reconfigurable Technol. Syst. 4 (4) (2011)
Andrew A. Kennings, Alan Mishchenko, Kristofer Vorwerk, Val Pevzner, Arun Kundu
Efficient FPGA Resynthesis Using Precomputed LUT Structures. FPL (2010)
Kristofer Vorwerk, Andrew A. Kennings, Val Pevzner, Arun Kundu, Madhu Raman, Julien Dunoyer, Yaun-shung Hsu
Power minimisation during field programmable gate array placement. IET Comput. Digit. Tech. 4 (3) (2010)
Kristofer Vorwerk, Andrew A. Kennings, Jonathan W. Greene
Improving Simulated Annealing-Based FPGA Placement With Directed Moves. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (2) (2009)
Val Pevzner, Andrew A. Kennings, Andy Fox
Physical optimization for FPGAs using post-placement topology rewriting. ISPD (2009)
Andrew A. Kennings, Kristofer Vorwerk, Arun Kundu, Val Pevzner, Andy Fox
FPGA technology mapping with encoded libraries andstaged priority cuts. FPGA (2009)
Kristofer Vorwerk, Madhu Raman, Julien Dunoyer, Yaun-Chung Hsu, Arun Kundu, Andrew A. Kennings
A technique for minimizing power during FPGA placement. FPL (2008)
Kristofer Vorwerk, Andrew A. Kennings, Doris T. Chen, Laleh Behjat
Floorplan repair using dynamic whitespace management. ACM Great Lakes Symposium on VLSI (2007)
Doris T. Chen, Kristofer Vorwerk, Andrew A. Kennings
Improving Timing-Driven FPGA Packing With Physical Information. FPL (2007)
Jianhua Li, Laleh Behjat, Andrew A. Kennings
Net Cluster: A Net-Reduction-Based Clustering Preprocessing Algorithm for Partitioning and Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (4) (2007)
Alexander Wong, Andrew A. Kennings
Adaptive multiple texture approach to texture packing for 3D video games. Future Play (2007)
Kristofer Vorwerk, Andrew A. Kennings, Jonathan W. Greene, Doris T. Chen
Improving Annealing Via Directed Moves. FPL (2007)
Andrew A. Kennings, Kristofer Vorwerk
Force-Directed Methods for Generic Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (10) (2006)
Kristofer Vorwerk, Andrew A. Kennings
An Improved Multi-Level Framework for Force-Directed Placement. DATE (2005)
Kristofer Vorwerk, Andrew A. Kennings
Mixed-size placement via line search. ICCAD (2005)
Miguel F. Anjos, Andrew A. Kennings, Anthony Vannelli
A semidefinite optimization approach for the single-row layout problem with unequal dimensions. Discret. Optim. 2 (2) (2005)
Austin Hung, William D. Bishop, Andrew A. Kennings
Symmetric Multiprocessing on Programmable Chips Made Easy. DATE (2005)
Kristofer Vorwerk, Andrew A. Kennings, Anthony Vannelli
Engineering details of a stable force-directed placer. ICCAD (2004)
William N. N. Hung, Xiaoyu Song, El Mostapha Aboulhamid, Andrew A. Kennings, Alan J. Coppola
Segmented channel routability via satisfiability. ACM Trans. Design Autom. Electr. Syst. 9 (4) (2004)
Austin Hung, William D. Bishop, Andrew A. Kennings
Enabling Cache Coherency for N-Way SMP Systems on Programmable Chips. ERSA (2004)
Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Andrew A. Kennings, Alan J. Coppola
Board-level multiterminal net assignment for the partial cross-bar architecture. IEEE Trans. Very Large Scale Integr. Syst. 11 (3) (2003)
Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Alan J. Coppola, Andrew A. Kennings
Board-level multiterminal net assignment. ACM Great Lakes Symposium on VLSI (2002)
William N. N. Hung, Xiaoyu Song, Alan J. Coppola, Andrew A. Kennings
On segmented channel routability. ISCAS (1) (2002)
Andrew A. Kennings, Igor L. Markov
Analytical minimization of half-perimeter wirelength. ASP-DAC (2000)
Andrew E. Caldwell, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov
Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting. DAC (1999)
Ross Baldick, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov
Function Smoothing with Applications to VLSI Layout. ASP-DAC (1999)