Power minimisation during field programmable gate array placement.
Kristofer VorwerkAndrew A. KenningsVal PevznerArun KunduMadhu RamanJulien DunoyerYaun-shung HsuPublished in: IET Comput. Digit. Tech. (2010)
Keyphrases
- field programmable gate array
- hardware implementation
- programmable logic
- embedded systems
- digital signal processors
- power consumption
- low power consumption
- image processing algorithms
- fpga device
- fpga technology
- parallel computing
- hardware architecture
- host computer
- software implementation
- pipelined architecture
- low power
- pattern recognition
- hardware design
- neural network
- hardware description language
- hw sw
- information systems
- hardware software
- bayesian networks
- computing systems
- energy efficiency
- object oriented
- efficient implementation