Jason Helge Anderson

Publication Activity (10 Years)

Years Active: 1998-2023
Publications (10 Years): 59

Top Venues

FPT

FPL

ASP-DAC

ACM Trans. Reconfigurable Technol. Syst.

Publications

Omar Ragheb, Rami Beidas, Jason Helge Anderson
Statically Scheduled vs. Elastic CGRA Architectures: Impact on Mapping Feasibility. IPDPS Workshops (2023)
Guanglei Zhou, Mirjana Stojilovic, Jason Helge Anderson
GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors. FPL (2023)
Guanglei Zhou, Jason Helge Anderson
Area-Driven FPGA Logic Synthesis Using Reinforcement Learning. ASP-DAC (2023)
Omar Ragheb, Tianyi Yu, Rami Beidas, Jason Helge Anderson
Elastic Multi-Context CGRAs. IPDPS Workshops (2022)
Rami Beidas, Jason Helge Anderson
CGRA Mapping Using Zero-Suppressed Binary Decision Diagrams. ASP-DAC (2022)
Hsuan Hsiao, Joshua San Miguel, Jason Helge Anderson
Streaming Accuracy: Characterizing Early Termination in Stochastic Computing. ASP-DAC (2022)
Omar Ragheb, Tianyi Yu, David Ma, Jason Helge Anderson
Modeling and Exploration of Elastic CGRAs. FPL (2022)
Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, John Wickerson, George A. Constantinides
Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code. IEEE Trans. Computers 71 (4) (2022)
Jason Helge Anderson, Rami Beidas, Vimal Chacko, Hsuan Hsiao, Xiaoyi Ling, Omar Ragheb, Xinyuan Wang, Tianyi Yu
CGRA-ME: An Open-Source Framework for CGRA Architecture and CAD Research : (Invited Paper). ASAP (2021)
Xiaoyi Ling, Takahiro Notsu, Jason Helge Anderson
An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator Systems. DSD (2021)
Hsuan Hsiao, Joshua San Miguel, Yuko Hara-Azumi, Jason Helge Anderson
Zero Correlation Error: A Metric for Finite-Length Bitstream Independence in Stochastic Computing. ASP-DAC (2021)
Austin Liolli, Omar Ragheb, Jason Helge Anderson
Profiling-Based Control-Flow Reduction in High-Level Synthesis. FPT (2021)
Xinyuan Wang, Tianyi Yu, Hsuan Hsiao, Jason Helge Anderson
Double-Pumping the Interconnect for Area Reduction in Coarse-Grained Reconfigurable Arrays. ASAP (2021)
Jin Hee Kim, Jason Helge Anderson
Post-LUT-Mapping Implementation of General Logic on Carry Chains Via a MIG-Based Circuit Representation. FPL (2021)
Omar Ragheb, Jason Helge Anderson
High-Level Synthesis of Transactional Memory. ASP-DAC (2021)
Kevin E. Murray, Jason Luu, Matthew J. P. Walker, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
Optimizing FPGA Logic Block Architectures for Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 28 (6) (2020)
Nicholas V. Giamblanco, Jason Helge Anderson
A Dynamic Memory Allocation Library for High-Level Synthesis. FPL (2019)
Matthew J. P. Walker, Jason Helge Anderson
Generic Connectivity-Based CGRA Mapping via Integer Linear Programming. FCCM (2019)
Nicholas V. Giamblanco, Jason Helge Anderson
ASAP: Automatic Sizing and Partitioning for Dynamic Memory Heaps in High-Level Synthesis. FPT (2019)
Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, George A. Constantinides
EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. FPGA (2019)
Matthew J. P. Walker, Jason Helge Anderson
Generic Connectivity-Based CGRA Mapping via Integer Linear Programming. CoRR (2019)
Hyeon Uk Sim, Jason Helge Anderson, Jongeun Lee
XOMA: exclusive on-chip memory architecture for energy-efficient deep learning acceleration. ASP-DAC (2019)
Hsuan Hsiao, Jason Helge Anderson
Thread Weaving: Static Resource Scheduling for Multithreaded High-Level Synthesis. DAC (2019)
Brett Grady, Jason Helge Anderson
Physical Design Considerations for Synthesizable Standard-Cell-Based FPGAs. HEART (2019)
Ian Taras, Jason Helge Anderson
Impact of FPGA Architecture on Area and Performance of CGRA Overlays. FCCM (2019)
Yu Ting Chen, Jin Hee Kim, Kexin Li, Graham Hoyes, Jason Helge Anderson
High-Level Synthesis Techniques to Generate Deeply Pipelined Circuits for FPGAs with Registered Routing. FPT (2019)
Omar Ragheb, Jason Helge Anderson
High-Level Synthesis of FPGA Circuits with Multiple Clock Domains. FCCM (2018)
Brett Grady, Jason Helge Anderson
Synthesizable Heterogeneous FPGA Fabrics. FPT (2018)
S. Alexander Chin, Jason Helge Anderson
An architecture-agnostic integer linear programming approach to CGRA mapping. DAC (2018)
Hsuan Hsiao, Jason Helge Anderson
Sensei: An area-reduction advisor for FPGA high-level synthesis. DATE (2018)
Jin Hee Kim, Jongeun Lee, Jason Helge Anderson
FPGA Architecture Enhancements for Efficient BNN Implementation. FPT (2018)
S. Alexander Chin, Kuang Ping Niu, Matthew J. P. Walker, Shizhang Yin, Alexander Mertens, Jongeun Lee, Jason Helge Anderson
Architecture Exploration of Standard-Cell and FPGA-Overlay CGRAs Using the Open-Source CGRA-ME Framework. ISPD (2018)
Jing Chen, Xue Liu, Jason Helge Anderson
Software-Specified FPGA Accelerators for Elementary Functions. FPT (2018)
Jongsok Choi, Ruolong Lian, Zhi Li, Andrew Canis, Jason Helge Anderson
Accelerating Memcached on AWS Cloud FPGAs. HEART (2018)
Samridhi Bansal, Hsuan Hsiao, Tomasz S. Czajkowski, Jason Helge Anderson
High-level synthesis of software-customizable floating-point cores. DATE (2018)
Jin Hee Kim, Brett Grady, Ruolong Lian, John Brothers, Jason Helge Anderson
FPGA-Based CNN Inference Accelerator Synthesized from Multi-Threaded C Software. CoRR (2018)
Kuang-Ping Niu, Jason Helge Anderson
Compact Area and Performance Modelling for CGRA Architecture Evaluation. FPT (2018)
Yu Ting Chen, Jason Helge Anderson
Automated generation of banked memory architectures in the high-level synthesis of multi-threaded software. FPL (2017)
Safeen Huda, Jason Helge Anderson
Leveraging Unused Resources for Energy Optimization of FPGA Interconnect. IEEE Trans. Very Large Scale Integr. Syst. 25 (8) (2017)
Jin Hee Kim, Brett Grady, Ruolong Lian, John Brothers, Jason Helge Anderson
FPGA-based CNN inference accelerator synthesized from multi-threaded C software. SoCC (2017)
Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang
The First 25 Years of the FPL Conference: Significant Papers. ACM Trans. Reconfigurable Technol. Syst. 10 (2) (2017)
Noriaki Sakamoto, Tanvir Ahmed, Jason Helge Anderson, Yuko Hara-Azumi
Subleq⊝: An Area-Efficient Two-Instruction-Set Computer. IEEE Embed. Syst. Lett. 9 (2) (2017)
S. Alexander Chin, Noriaki Sakamoto, Allan Rui, Jim Zhao, Jin Hee Kim, Yuko Hara-Azumi, Jason Helge Anderson
CGRA-ME: A unified framework for CGRA modelling and exploration. ASAP (2017)
Jin Hee Kim, Jason Helge Anderson
Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow. ACM Trans. Reconfigurable Technol. Syst. 10 (2) (2017)
Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson
From Pthreads to Multicore Hardware Systems in LegUp High-Level Synthesis for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 25 (10) (2017)
Charles Eric LaForest, Jason Helge Anderson
Microarchitectural Comparison of the MXP and Octavo Soft-Processor FPGA Overlays. ACM Trans. Reconfigurable Technol. Syst. 10 (3) (2017)
Safeen Huda, Jason Helge Anderson
Towards PVT-Tolerant Glitch-Free Operation in FPGAs. FPGA (2016)
S. Alexander Chin, Jason Luu, Safeen Huda, Jason Helge Anderson
Hybrid LUT/Multiplexer FPGA Logic Architectures. IEEE Trans. Very Large Scale Integr. Syst. 24 (4) (2016)
Jongsok Choi, Ruolong Lian, Stephen Dean Brown, Jason Helge Anderson
A unified software approach to specify pipeline and spatial parallelism in FPGA hardware. ASAP (2016)
Safeen Huda, Jason Helge Anderson
Power Optimization of FPGA Interconnect Via Circuit and CAD Techniques. ISPD (2016)
Jason Helge Anderson, Yuko Hara-Azumi, Shigeru Yamashita
Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy. DATE (2016)
Razvan Nane, Vlad Mihai Sima, Christian Pilato, Jongsok Choi, Blair Fort, Andrew Canis, Yu Ting Chen, Hsuan Hsiao, Stephen Dean Brown, Fabrizio Ferrandi, Jason Helge Anderson, Koen Bertels
A Survey and Evaluation of FPGA High-Level Synthesis Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (10) (2016)
Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele
Preface. FPL (2016)
Stefan Hadjis, Andrew Canis, Ryoya Sobue, Yuko Hara-Azumi, Hiroyuki Tomiyama, Jason Helge Anderson
Profiling-driven multi-cycling in FPGA high-level synthesis. DATE (2015)
Tanvir Ahmed, Noriaki Sakamoto, Jason Helge Anderson, Yuko Hara-Azumi
Synthesizable-from-C Embedded Processor Based on MIPS-ISA and OISC. EUC (2015)
Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson
The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware. ACM Trans. Reconfigurable Technol. Syst. 8 (3) (2015)
Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson
Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware. FPT (2015)
Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang
Significant papers from the first 25 years of the FPL conference. FPL (2015)
Jin Hee Kim, Jason Helge Anderson
Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow. FPL (2015)
Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson
Source-level debugging for FPGA high-level synthesis. FPL (2014)
Safeen Huda, Jason Helge Anderson, Hirotaka Tamura
Optimizing effective interconnect capacitance for FPGA power reduction. FPGA (2014)
Tahir Diop, Natalie D. Enright Jerger, Jason Helge Anderson
Power Modeling for Heterogeneous Processors. GPGPU@ASPLOS (2014)
Jason Helge Anderson, Kiyoung Choi
International Conference on Field-Programmable Technology (FPT'12). ACM Trans. Reconfigurable Technol. Syst. 7 (3) (2014)
Jason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
On Hard Adders and Carry Chains in FPGAs. FCCM (2014)
Charles Eric LaForest, Jason Helge Anderson, J. Gregory Steffan
Approaching overhead-free execution on FPGA soft-processors. FPT (2014)
Marcel Gort, Jason Helge Anderson
Design re-use for compile time reduction in FPGA high-level synthesis flows. FPT (2014)
Andrew Canis, Stephen Dean Brown, Jason Helge Anderson
Modulo SDC scheduling with recurrence minimization in high-level synthesis. FPL (2014)
Blair Fort, Andrew Canis, Jongsok Choi, Nazanin Calagar, Ruolong Lian, Stefan Hadjis, Yu Ting Chen, Mathew Hall, Bain Syrowik, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson
Automating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis. EUC (2014)
Jason Luu, Jonathan Rose, Jason Helge Anderson
Towards interconnect-adaptive packing for FPGAs. FPGA (2014)
Jason Luu, Jeffrey Goeders, Michael Wainberg, Andrew Somerville, Thien Yu, Konstantin Nasartschuk, Miad Nasr, Sen Wang, Tim Liu, Nooruddin Ahmed, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
VTR 7.0: Next Generation Architecture and CAD System for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 7 (2) (2014)
S. Alexander Chin, Jason Helge Anderson
A case for hardened multiplexers in FPGAs. FPT (2013)
Safeen Huda, Jason Helge Anderson, Hirotaka Tamura
Charge recycling for power reduction in FPGA interconnect. FPL (2013)
Jiu Cheng Cai, Ruolong Lian, Mengyao Wang, Andrew Canis, Jongsok Choi, Blair Fort, Eric Hart, Emily Miao, Yanyan Zhang, Nazanin Calagar, Stephen Dean Brown, Jason Helge Anderson
From C to Blokus Duo with LegUp high-level synthesis. FPT (2013)
Ana Klimovic, Jason Helge Anderson
Bitwidth-optimized hardware accelerators with software fallback. FPT (2013)
Andrew Canis, Jongsok Choi, Blair Fort, Ruolong Lian, Qijing Huang, Nazanin Calagar, Marcel Gort, Jia Jun Qin, Mark Aldham, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson
From software to accelerators with LegUp high-level synthesis. CASES (2013)
Jason Helge Anderson, Stephen Dean Brown, Andrew Canis, Jongsok Choi
High-level synthesis with LegUp: a crash course for users and researchers. FPGA (2013)
Marcel Gort, Jason Helge Anderson
Range and bitmask analysis for hardware optimization in high-level synthesis. ASP-DAC (2013)
Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Tomasz S. Czajkowski, Stephen Dean Brown, Jason Helge Anderson
LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems. ACM Trans. Embed. Comput. Syst. 13 (2) (2013)
Tahir Diop, Steven Gurfinkel, Jason Helge Anderson, Natalie D. Enright Jerger
DistCL: A Framework for the Distributed Execution of OpenCL Kernels. MASCOTS (2013)
Andrew Canis, Jason Helge Anderson, Stephen Dean Brown
Multi-pumping for resource reduction in FPGA high-level synthesis. DATE (2013)
Bill Teng, Jason Helge Anderson
Latch-Based Performance Optimization for Field-Programmable Gate Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (5) (2013)
Marcel Gort, Jason Helge Anderson
Combined Architecture/Algorithm Approach to Fast FPGA Routing. IEEE Trans. Very Large Scale Integr. Syst. 21 (6) (2013)
Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Stephen Dean Brown, Jason Helge Anderson
The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs. FCCM (2013)
Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson
From software threads to parallel hardware in high-level synthesis for FPGAs. FPT (2013)
Edgar Mora-Sanchez, Jason Helge Anderson
Leakage power reduction in FPGA DSP circuits through algorithmic noise tolerance. ReConFig (2013)
Warren Wai-Kit Shum, Jason Helge Anderson
Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power. FPGA (2012)
Stefan Hadjis, Andrew Canis, Jason Helge Anderson, Jongsok Choi, Kevin Nam, Stephen Dean Brown, Tomasz S. Czajkowski
Impact of FPGA architecture on resource sharing in high-level synthesis. FPGA (2012)
Zissis Poulos, Yu-Shen Yang, Jason Helge Anderson, Andreas G. Veneris, Bao Le
Leveraging reconfigurability to raise productivity in FPGA functional debug. DATE (2012)
Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson
The VTR project: architecture and CAD for FPGAs from verilog to routing. FPGA (2012)
Marcel Gort, Jason Helge Anderson
Analytical placement for heterogeneous FPGAs. FPL (2012)
Jongsok Choi, Kevin Nam, Andrew Canis, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski
Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems. FCCM (2012)
Chirag Ravishankar, Jason Helge Anderson, Andrew A. Kennings
FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (9) (2012)
Chirag Ravishankar, Andrew A. Kennings, Jason Helge Anderson
FPGA power reduction by guarded evaluation considering physical information. VLSI-SoC (2012)
Marcel Gort, Jason Helge Anderson
Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (1) (2012)
Jason Helge Anderson, Qiang Wang, Chirag Ravishankar
Raising FPGA Logic Density Through Synthesis-Inspired Architecture. IEEE Trans. Very Large Scale Integr. Syst. 20 (3) (2012)
Marcel Gort, Jason Helge Anderson
Reducing FPGA Router Run-Time through Algorithm and Architecture. FPL (2011)
Jason Helge Anderson, Qiang Wang
Area-efficient FPGA logic elements: Architecture and synthesis. ASP-DAC (2011)
Mark Aldham, Jason Helge Anderson, Stephen Dean Brown, Andrew Canis
Low-cost hardware profiling of run-time and energy in FPGA embedded processors. ASAP (2011)
Jason Luu, Jason Helge Anderson, Jonathan Rose
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect. FPGA (2011)
Alireza Rakhshanfar, Jason Helge Anderson
An integer programming placement approach to FPGA clock power reduction. ASP-DAC (2011)

Jason Helge Anderson.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Jason Helge Anderson