Reducing FPGA Router Run-Time through Algorithm and Architecture.
Marcel GortJason Helge AndersonPublished in: FPL (2011)
Keyphrases
- hardware implementation
- real time
- computational complexity
- experimental evaluation
- dynamic programming
- neural network
- detection algorithm
- high accuracy
- worst case
- parallel architecture
- k means
- probabilistic model
- hardware architecture
- optimal solution
- cost function
- convergence rate
- times faster
- objective function
- optimization algorithm
- segmentation algorithm
- software implementation
- input data
- fpga implementation
- computational cost
- preprocessing
- significant improvement
- dedicated hardware
- pipelined architecture
- image processing algorithms
- recognition algorithm
- matching algorithm
- theoretical analysis
- linear programming
- data structure
- learning algorithm