Optimizing FPGA Logic Block Architectures for Arithmetic.
Kevin E. MurrayJason LuuMatthew J. P. WalkerConor McCulloughSen WangSafeen HudaBo YanCharles ChiassonKenneth B. KentJason Helge AndersonJonathan RoseVaughn BetzPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2020)
Keyphrases
- micron cmos
- pipelined architecture
- high speed
- modal logic
- hardware implementation
- logical framework
- classical logic
- field programmable gate array
- automated reasoning
- logic programming
- predicate logic
- low cost
- multi valued
- image processing
- asynchronous circuits
- proof theory
- dct coefficients
- hardware design
- single chip
- parallel architectures
- deontic logic
- fpga implementation
- signal processing