Jonathan Rose

ORCID

Publication Activity (10 Years)

Years Active: 1985-2024
Publications (10 Years): 14

Top Venues

ACM Trans. Reconfigurable Technol. Syst.

FPGA

FCCM

CoRR

Publications

Andrew Brown, Jiading Zhu, Mohamed Abdelwahab, Alec Dong, Cindy Wang, Jonathan Rose
Generation, Distillation and Evaluation of Motivational Interviewing-Style Reflections with a Foundational Language Model. CoRR (2024)
Andrew Brown, Jiading Zhu, Mohamed Abdelwahab, Alec Dong, Cindy Wang, Jonathan Rose
Generation, Distillation and Evaluation of Motivational Interviewing-Style Reflections with a Foundational Language Model. EACL (1) (2024)
Rohan Deepak Ajwani, Zining Zhu, Jonathan Rose, Frank Rudzicz
Plug and Play with Prompts: A Prompt Tuning Approach for Controlling Text Generation. CoRR (2024)
Kevin E. Murray, Jason Luu, Matthew J. P. Walker, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
Optimizing FPGA Logic Block Architectures for Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 28 (6) (2020)
Soumil Chugh, Braiden Brousseau, Jonathan Rose, Moshe Eizenman
Detection and Correspondence Matching of Corneal Reflections for Eye Tracking Using Deep Learning. ICPR (2020)
Braiden Brousseau, Jonathan Rose, Moshe Eizenman
Hybrid Eye-Tracking on a Smartphone with CNN Feature Extraction and an Infrared 3D Model. Sensors 20 (2) (2020)
Henry Wong, Vaughn Betz, Jonathan Rose
High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors. ACM Trans. Reconfigurable Technol. Syst. 11 (1) (2018)
Alex Rodionov, Jonathan Rose
Automatic Topology Optimization for FPGA Interconnect Synthesis. FPL (2018)
Braiden Brousseau, Jonathan Rose, Moshe Eizenman
SmartEye: An Accurate Infrared Eye Tracking System for Smartphones. UEMCON (2018)
Alex Rodionov, Jonathan Rose
Synchronization Constraints for Interconnect Synthesis. FPGA (2017)
Fitsum Assamnew Andargie, Jonathan Rose, Todd M. Austin, Valeria Bertacco
Energy efficient object detection on the mobile GP-GPU. AFRICON (2017)
Henry Wong, Vaughn Betz, Jonathan Rose
High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors. FCCM (2016)
Alex Rodionov, David Biancolin, Jonathan Rose
Fine-Grained Interconnect Synthesis. ACM Trans. Reconfigurable Technol. Syst. 9 (4) (2016)
Henry Wong, Vaughn Betz, Jonathan Rose
Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System. ACM Trans. Reconfigurable Technol. Syst. 10 (1) (2016)
Alex Rodionov, Jonathan Rose
Automatic FPGA system and interconnect construction with multicast and customizable topology. FPT (2015)
Alex Rodionov, David Biancolin, Jonathan Rose
Fine-Grained Interconnect Synthesis. FPGA (2015)
Fitsum Assamnew Andargie, Jonathan Rose
Performance characterization of mobile GP-GPUs. AFRICON (2015)
Henry Wong, Vaughn Betz, Jonathan Rose
Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design. IEEE Trans. Very Large Scale Integr. Syst. 22 (10) (2014)
Jason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
On Hard Adders and Carry Chains in FPGAs. FCCM (2014)
Jason Luu, Jonathan Rose, Jason Helge Anderson
Towards interconnect-adaptive packing for FPGAs. FPGA (2014)
Jason Luu, Jeffrey Goeders, Michael Wainberg, Andrew Somerville, Thien Yu, Konstantin Nasartschuk, Miad Nasr, Sen Wang, Tim Liu, Nooruddin Ahmed, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz
VTR 7.0: Next Generation Architecture and CAD System for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 7 (2) (2014)
Henry Wong, Vaughn Betz, Jonathan Rose
Efficient methods for out-of-order load/store execution for high-performance soft processors. FPT (2013)
Niyati Shah, Jonathan Rose
On the difficulty of pin-to-wire routing in FPGAs. FPL (2012)
Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson
The VTR project: architecture and CAD for FPGAs from verilog to routing. FPGA (2012)
Braiden Brousseau, Jonathan Rose
An energy-efficient, fast FPGA hardware architecture for OpenCV-Compatible object detection. FPT (2012)
Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
Portable, Flexible, and Scalable Soft Vector Processors. IEEE Trans. Very Large Scale Integr. Syst. 20 (8) (2012)
Wei Zhang, Vaughn Betz, Jonathan Rose
Portable and scalable FPGA-based acceleration of a direct linear system solver. ACM Trans. Reconfigurable Technol. Syst. 5 (1) (2012)
Jason Luu, Jason Helge Anderson, Jonathan Rose
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect. FPGA (2011)
Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, Kenneth B. Kent, Jonathan Rose
VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling. ACM Trans. Reconfigurable Technol. Syst. 4 (4) (2011)
Henry Wong, Vaughn Betz, Jonathan Rose
Comparing FPGA vs. custom cmos and the impact on processor microarchitecture. FPGA (2011)
Jonathan Rose, Guy G. Lemieux
The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop. FPGA (2011)
Alex Rodionov, Alexandr Bezginov, Jonathan Rose, Elisabeth R. M. Tillier
A new, fast algorithm for detecting protein coevolution using maximum compatible cliques. Algorithms Mol. Biol. 6 (2011)
Ian Kuon, Jonathan Rose
Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design. IEEE Trans. Very Large Scale Integr. Syst. 19 (1) (2011)
Alex Rodionov, Alexandr Bezginov, Jonathan Rose, Elisabeth R. M. Tillier
Faster coevolution detection of proteins using maximum similar cliques. BCB (2010)
Peter A. Jamieson, Jonathan Rose
Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters. IEEE Trans. Very Large Scale Integr. Syst. 18 (12) (2010)
Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, Jonathan Rose
VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. FPGA (2009)
Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
Fine-grain performance scaling of soft vector processors. CASES (2009)
Jonathan Rose
The evolution of architecture exploration of programmable devices. FPL (2009)
Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
Soft vector processors vs FPGA custom hardware: measuring and reducing the gap. FPGA (2009)
Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
Data parallel FPGA workloads: Software versus hardware. FPL (2009)
Jason Luu, Keith Redmond, William Lo, Paul Chow, Lothar Lilge, Jonathan Rose
FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy. FCCM (2009)
Wei Zhang, Vaughn Betz, Jonathan Rose
Portable and scalable FPGA-based acceleration of a direct linear system solver. FPT (2008)
Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
VESPA: portable, scalable, and flexible FPGA-based vector processors. CASES (2008)
Ian Kuon, Jonathan Rose
Automated transistor sizing for FPGA architecture exploration. DAC (2008)
Ian Kuon, Jonathan Rose
Area and delay trade-offs in the circuit and architecture design of FPGAs. FPGA (2008)
Wei Mark Fang, Jonathan Rose
Modeling routing demand for early-stage FPGA architecture development. FPGA (2008)
Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
Exploration and Customization of FPGA-Based Soft Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (2) (2007)
Peter Jamieson, Jonathan Rose
Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency with Shadow Clusters. FPT (2007)
Ian Kuon, Jonathan Rose
Measuring the Gap Between FPGAs and ASICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (2) (2007)
Ian Kuon, Russell Tessier, Jonathan Rose
FPGA Architecture: Survey and Challenges. Found. Trends Electron. Des. Autom. 2 (2) (2007)
Ian Kuon, Jonathan Rose
Measuring the gap between FPGAs and ASICs. FPGA (2006)
Andy Gean Ye, Jonathan Rose
Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits. IEEE Trans. Very Large Scale Integr. Syst. 14 (5) (2006)
Jonathan Rose
Invited Keynote 1: Closing the gap between FPGAs and ASICs. FPT (2006)
Ahmad Darabiha, W. James MacLean, Jonathan Rose
Reconfigurable hardware implementation of a phase-correlation stereoalgorithm. Mach. Vis. Appl. 17 (2) (2006)
Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose
Application-specific customization of soft processor microarchitecture. FPGA (2006)
Peter Jamieson, Jonathan Rose
Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters. FPT (2006)
Ian Kuon, Aaron Egier, Jonathan Rose
Design, layout and verification of an FPGA using automated tools. FPGA (2005)
Andy Gean Ye, Jonathan Rose
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits. FPGA (2005)
Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan
The microarchitecture of FPGA-based soft processors. CASES (2005)
Joshua Fender, Jonathan Rose, David R. Galloway
The Transmogrifier-4: An FPGA-Based Hardware Development System with Multi-Gigabyte Memory Capacity and High Host and Memory Bandwidth. FPT (2005)
Andy Gean Ye, Jonathan Rose
Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks. FPL (2005)
David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose
The Stratix II logic and routing architecture. FPGA (2005)
Peter Jamieson, Jonathan Rose
A Verilog RTL Synthesis Tool for Heterogeneous FPGAs. FPL (2005)
Elias Ahmed, Jonathan Rose
The effect of LUT and cluster size on deep-submicron FPGA performance and density. IEEE Trans. Very Large Scale Integr. Syst. 12 (3) (2004)
Anish Alex, Jonathan Rose, Ruth Isserlin-Weinberger, Christopher W. V. Hogue
Hardware Accelerated Novel Protein Identification. FPL (2004)
Ian Kuon, Aaron Egier, Jonathan Rose
Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs. FPGA (2004)
Tomasz S. Czajkowski, Jonathan Rose
A synthesis oriented omniscient manual editor. FPGA (2004)
Paul D. Kundarewich, Jonathan Rose
Synthetic circuit generation using clustering and iteration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (6) (2004)
Jonathan Rose
Hard vs. Soft: The Central Question of Pre-Fabricated Silicon. ISMVL (2004)
Andy Gean Ye, Jonathan Rose
Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits. FPT (2004)
Joshua Fender, Jonathan Rose
A high-speed ray tracing engine built on a field-programmable system. FPT (2003)
Paul D. Kundarewich, Jonathan Rose
Synthetic circuit generation using clustering and iteration. FPGA (2003)
Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose
Automatic transistor and physical design of FPGA tiles from an architectural specification. FPGA (2003)
David M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose
routing and logic architecture. FPGA (2003)
Ahmad Darabiha, Jonathan Rose, W. James MacLean
Video-Rate Stereo Depth Measurement on Programmable Hardware. CVPR (1) (2003)
Peter Yiannacouras, Jonathan Rose
A parameterized automatic cache generator for FPGAs. FPT (2003)
Michael D. Hutton, Jonathan Rose, Derek G. Corneil
Automatic generation of synthetic sequential benchmark circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (8) (2002)
Ajay Roopchansingh, Jonathan Rose
Nearest neighbour interconnect architecture in deep submicron FPGAs. CICC (2002)
William Chow, Jonathan Rose
EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits. FPGA (2002)
Andy Ye, Jonathan Rose, David M. Lewis
Synthesizing datapath circuits for FPGAs with emphasis on area minimization. FPT (2002)
Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen
Panel: (When) Will FPGAs Kill ASICs? DAC (2001)
Mike Sheng, Jonathan Rose
Mixing buffers and pass transistors in FPGA routing architectures. FPGA (2001)
Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
Structural analysis and generation of synthetic digital circuits with memory. IEEE Trans. Very Large Scale Integr. Syst. 9 (1) (2001)
Alexander Marquardt, Vaughn Betz, Jonathan Rose
Timing-driven placement for FPGAs. FPGA (2000)
Elias Ahmed, Jonathan Rose
The effect of LUT and cluster size on deep-submicron FPGA performance and density. FPGA (2000)
Vaughn Betz, Jonathan Rose
Automatic generation of FPGA routing architectures from high-level descriptions. FPGA (2000)
Alexander Marquardt, Vaughn Betz, Jonathan Rose
Speed and area tradeoffs in cluster-based FPGA architectures. IEEE Trans. Very Large Scale Integr. Syst. 8 (1) (2000)
Mohammed A. S. Khalid, Jonathan Rose
A novel and efficient routing architecture for multi-FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. 8 (1) (2000)
Rob McCready, Jonathan Rose
Real-time, frame-rate face detection on a configurable hardware system (poster abstract). FPGA (2000)
Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic
The memory/logic interface in FPGAs with large embedded memory arrays. IEEE Trans. Very Large Scale Integr. Syst. 7 (1) (1999)
Vaughn Betz, Jonathan Rose
FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density. FPGA (1999)
Yaska Sankar, Jonathan Rose
Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs. FPGA (1999)
Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, Immanuel Rahardja
The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout. IEEE Trans. Very Large Scale Integr. Syst. 7 (3) (1999)
Alexander Marquardt, Vaughn Betz, Jonathan Rose
Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density. FPGA (1999)
Michael D. Hutton, Jonathan Rose
Applications of clone circuits to issues in physical-design. ISCAS (6) (1999)
Mohammed A. S. Khalid, Jonathan Rose
Hardwired-Clusters Partial-Crossbar: A Hierarchical Routing Architecture for Multi-FPGA Systems. IPPS/SPDP Workshops (1999)
Michael D. Hutton, Jonathan Rose
Equivalence classes of clone circuits for physical-design benchmarking. ISCAS (6) (1999)
Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, Immanuel Rahardja
The design of an SRAM-based field-programmable gate array. I. Architecture. IEEE Trans. Very Large Scale Integr. Syst. 7 (2) (1999)
Mohammed A. S. Khalid, Jonathan Rose
A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems. FPGA (1998)
Michael D. Hutton, Jonathan Rose, Jerry P. Grossman, Derek G. Corneil
Characterization and parameterized generation of synthetic combinational benchmark circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (10) (1998)

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Publication Activity (10 Years)

Top Topics

Top Venues

Jonathan Rose