Carl Sechen

Publication Activity (10 Years)

Years Active: 1986-2024
Publications (10 Years): 15

Top Topics

Dynamic Reconfiguration

Energy Landscape

General Purpose Processors

Top Venues

Publications

Apurva Jain, Thomas Broadfoot, Carl Sechen, Yiorgos Makris
Testing a Transistor-Level Programmable Fabric: Challenges and Solutions. VTS (2024)
Apurva Jain, Thomas Broadfoot, Yiorgos Makris, Carl Sechen
Quo Vadis Signal? Automated Directionality Extraction for Post-Programming Verification of a Transistor-Level Programmable Fabric. DATE (2023)
Vibhav Kumarswami Salimath, Carl Sechen
Optimal Standard Cell Library Composition for 7nm. ISCAS (2020)
Mustafa Munawar Shihab, Bharath Ramanidharan, Suraag Sunil Tellakula, Gaurav Rajavendra Reddy, Jingxiang Tian, Carl Sechen, Yiorgos Makris
ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable Fabric. VTS (2020)
Bo Hu, Mustafa M. Shihab, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen
An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAs. DATE (2020)
Mustafa M. Shihab, Bharath Ramanidharan, Gaurav Rajavendra Reddy, Jingxiang Tian, William Swartz, Carl Sechen, Yiorgos Makris
CASPER: CAD Framework for a Novel Transistor-Level Programmable Fabric. ISCAS (2020)
Bo Hu, Jingxiang Tian, Mustafa M. Shihab, Gaurav Rajavendra Reddy, William Swartz, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen
Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA. ACM Great Lakes Symposium on VLSI (2019)
Bo Hu, Mustafa M. Shihab, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen
Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage. FPT (2019)
Mustafa M. Shihab, Jingxiang Tian, Gaurav Rajavendra Reddy, Bo Hu, William Swartz, Benjamin Carrión Schäfer, Carl Sechen, Yiorgos Makris
Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming. DATE (2019)
Tutu Ajayi, Vidya A. Chhabria, Mateus Fogaça, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Minsoo Kim, Jeongsup Lee, Uday Mallappa, Marina Neseem, Geraldo Pradipta, Sherief Reda, Mehdi Saligane, Sachin S. Sapatnekar, Carl Sechen, Mohamed Shalan, William Swartz, Lutong Wang, Zhehong Wang, Mingyu Woo, Bangqi Xu
Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project. DAC (2019)
Meisam Heidarpour Roshan, Samira Zaliasl, Kimo Joo, Kamran Souri, Rajkumar Palwai, Lijun Will Chen, Amanpreet Singh, Sudhakar Pamarti, Nicholas Miller, Joseph C. Doll, Carl Arft, Sassan Tabatabaei, Carl Sechen, Aaron Partridge, Vinod Menon
A MEMS-Assisted Temperature Sensor With 20-µK Resolution, Conversion Rate of 200 S/s, and FOM of 0.04 pJK2. IEEE J. Solid State Circuits 52 (1) (2017)
Anitha Kumari Yella, Gunturi Srivatsa, Carl Sechen
Are standalone gate size and VT optimization tools useful? CCECE (2017)
Jingxiang Tian, Gaurav Rajavendra Reddy, Jiajia Wang, William Swartz, Yiorgos Makris, Carl Sechen
A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration. DATE (2017)
Thomas Broadfoot, Carl Sechen, Jeyavijayan (JV) Rajendran
On designing optimal camouflaged layouts. HOST (2017)
Meisam Heidarpour Roshan, Samira Zali Asl, Kimo Joo, Kamran Souri, Rajkumar Palwai, Lijun Will Chen, Sudhakar Pamarti, Joseph C. Doll, Nicholas Miller, Carl Arft, Sassan Tabatabaei, Carl Sechen, Aaron Partridge, Vinod Menon
11.1 Dual-MEMS-resonator temperature-to-digital converter with 40 K resolution and FOM of 0.12pJK2. ISSCC (2016)
Zhao Wang, Xiao He, Carl Sechen
A New Approach for Gate-Level Delay-Insensitive Asynchronous Logic. Circuits Syst. Signal Process. 34 (5) (2015)
Mohammad Rahman, Hiran Tennakoon, Carl Sechen
Library-Based Cell-Size Selection Using Extended Logical Effort. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (7) (2013)
Akshay Sridharan, Carl Sechen, Roozbeh Jafari
Low-voltage low-overhead asynchronous logic. ISLPED (2013)
Mohammad Rahman, Carl Sechen
Post-synthesis leakage power minimization. DATE (2012)
Chiu-wei Pan, Zhao Wang, Yuanchen Song, Carl Sechen
Power efficient partial product compression. ACM Great Lakes Symposium on VLSI (2011)
Mohammad Rahman, Hiran Tennakoon, Carl Sechen
Power reduction via near-optimal library-based cell-size selection. DATE (2011)
Mohammad Rahman, Ryan Afonso, Hiran Tennakoon, Carl Sechen
Power reduction via separate synthesis and physical libraries. DAC (2011)
Hiran Tennakoon, Carl Sechen
Nonconvex Gate Delay Modeling and Delay Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (9) (2008)
Sheng Sun, Carl Sechen
Post-layout comparison of high performance 64b static adders in energy-delay space. ICCD (2007)
Kian Haur Chong, Larry McMurchie, Carl Sechen
A 64b adder using self-calibrating differential output prediction logic. ISSCC (2006)
Jinyao Zhang, Miodrag Vujkovic, David Wadkins, Carl Sechen
Post-layout energy-delay analysis of parallel multipliers. ISCAS (2006)
Xinyu Guo, Carl Sechen
A high throughput divider implementation. CICC (2005)
Xinyu Guo, Carl Sechen
High Speed Redundant Adder and Divider in Output Prediction Logic. ISVLSI (2005)
Sheng Sun, Yi Han, Xinyu Guo, Kian Haur Chong, Larry McMurchie, Carl Sechen
409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS. ISVLSI (2005)
Miodrag Vujkovic, David Wadkins, Carl Sechen
Efficient Post-layout Power-Delay Curve Generation. PATMOS (2005)
Hiran Tennakoon, Carl Sechen
Efficient and accurate gate sizing with piecewise convex delay models. DAC (2005)
Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen
Efficient timing closure without timing driven placement and routing. DAC (2004)
Yi Han, Larry McMurchie, Carl Sechen
A high performance CMOS programmable logic core. CICC (2004)
Carl Sechen, Barbara Chappel, Jim Hogan, Andrew Moore, Tadahiko Nakamura, Gregory A. Northrop, Anjaneya Thakar
Libraries: lifejacket or straitjacket. DAC (2003)
Su Kio, Kian Haur Chong, Carl Sechen
A low power delayed-clocks generation and distribution system. ISCAS (5) (2003)
Jovanka Ciric, Carl Sechen
Efficient canonical form for Boolean matching of complex functions in large libraries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (5) (2003)
Miodrag Vujkovic, Carl Sechen
Optimized power-delay curve generation for standard cell ICs. ICCAD (2002)
G. N. Hoyer, Gin Yee, Carl Sechen
Locally clocked pipelines and dynamic logic. IEEE Trans. Very Large Scale Integr. Syst. 10 (1) (2002)
Hiran Tennakoon, Carl Sechen
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. ICCAD (2002)
Larry McMurchie, Carl Sechen
WTA: waveform-based timing analysis for deep submicron circuits. ICCAD (2002)
Miodrag Vujkovic, Carl Sechen
Optimized Power-Delay Curve Generation for Standard Cell ICs. IWLS (2002)
Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen
Panel: (When) Will FPGAs Kill ASICs? DAC (2001)
Tatjana Serdar, Carl Sechen
Automatic datapath tile placement and routing. DATE (2001)
Sheng Sun, Larry McMurchie, Carl Sechen
A High-Performance 64-bit Adder Implemented in Output Prediction Logic. ARVLSI (2001)
Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen
Timing- and crosstalk-driven area routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (4) (2001)
Jovanka Ciric, Carl Sechen
Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries. ICCAD (2001)
Gin Yee, Tyler Thorp, Ron Christopherson, Ban P. Wang, Carl Sechen
An Automated Shielding Algorithm and Tool For Dynamic Circuits. ISQED (2000)
Gin Yee, Carl Sechen
Clock-delayed domino for dynamic circuit design. IEEE Trans. Very Large Scale Integr. Syst. 8 (4) (2000)
Gregg N. Hoyer, Carl Sechen
A locally-clocked dynamic logic serial/parallel multiplier. CICC (2000)
Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen
Output Prediction Logic: A High-Performance CMOS Design Technique. ICCD (2000)
Jovanka Ciric, Gin Yee, Carl Sechen
Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. DATE (2000)
Hsiao-Ping Tseng, Carl Sechen
A gridless multilayer router for standard cell circuits using CTMcells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (10) (1999)
Le-Chin Eugene Liu, Carl Sechen
Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (10) (1999)
Le-Chin Eugene Liu, Carl Sechen
Multilayer pin assignment for macro cell circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18 (10) (1999)
Tyler Thorp, Gin Yee, Carl Sechen
Design and Synthesis of Monotonic Circuits. ICCD (1999)
Tatjana Serdar, Carl Sechen
AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths. ICCAD (1999)
Tyler Thorp, Gin Yee, Carl Sechen
Domino logic synthesis using complex static gates. ICCAD (1998)
Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen
Timing and Crosstalk Driven Area Routing. DAC (1998)
Le-Chin Eugene Liu, Hsiao-Ping Tseng, Carl Sechen
Chip-level area routing. ISPD (1998)
Qicheng Yu, Carl Sechen
Efficient approximation of symbolic network functions using matroid intersection algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (10) (1997)
Wern-Jieh Sun, Carl Sechen
A parallel standard cell placement algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16 (11) (1997)
Martin Lefebvre, David Marple, Carl Sechen
The Future of Custom Cell Generation in Physical Synthesis. DAC (1997)
Hsiao-Ping Tseng, Carl Sechen
A gridless multi-layer router for standard cell circuits using CTM cells. ED&TC (1997)
Le-Chin Eugene Liu, Carl Sechen
Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic. ED&TC (1997)
Bingzhong Guan, Carl Sechen
Large Standard Cell Libraries and Their Impact on Layout Area and Circuit Performanc. ICCD (1996)
Kalapi Roy-Neogi, Bingzhong Guan, Carl Sechen
A Sea-of-Gates Style FPGA Placement Algorithm. VLSI Design 4 (4) (1996)
Kalapi Roy-Neogi, Carl Sechen
A Timing-Driven Partitioning System for Multiple FPGAs. VLSI Design 4 (4) (1996)
Qicheng Yu, Carl Sechen
Generation of colour-constrained spanning trees with application in symbolic circuit analysis. Int. J. Circuit Theory Appl. 24 (5) (1996)
Gin Yee, Carl Sechen
Clock-Delayed Domino for Adder and Combinational Logic Desig. ICCD (1996)
Kalapi Roy-Neogi, Carl Sechen
Multiple FPGA Partitioning with Performance Optimization. FPGA (1995)
Ted Stanion, Carl Sechen
A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis. DAC (1995)
Wern-Jieh Sun, Carl Sechen
Efficient and effective placement for very large circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (3) (1995)
William Swartz, Carl Sechen
Timing Driven Placement for Large Standard Cell Circuits. DAC (1995)
Ted Stanion, Carl Sechen
Quasi-algebraic decompositions of switching functions. ARVLSI (1995)
Ted Stanion, Debashis Bhattacharya, Carl Sechen
An efficient method for generating exhaustive test sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (12) (1995)
Qicheng Yu, Carl Sechen
Efficient Approximation of Symbolic Network Function Using Matroid Intersection Algorithms. ISCAS (1995)
Jer-Jaw Hsu, Carl Sechen
Accurate Extraction of Simplified Symbolic Pole/Zero Expressions for Large Analog IC's. ISCAS (1995)
Qicheng Yu, Carl Sechen
Approximate symbolic analysis of large analog integrated circuits. ICCAD (1994)
Qicheng Yu, Carl Sechen
Generation of color-constrained spanning trees with application in symbolic circuit analysis. Great Lakes Symposium on VLSI (1994)
Kalapi Roy-Neogi, Bingzhong Guan, Carl Sechen
A Sea-of-Gates Style FPGA Placement Algorithm. VLSI Design (1994)
Ted Stanion, Carl Sechen
Boolean division and factorization using binary decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (9) (1994)
Wern-Jieh Sun, Carl Sechen
A loosely coupled parallel algorithm for standard cell placement. ICCAD (1994)
Ted Stanion, Carl Sechen
Maximum projections of don't care conditions in a Boolean network. ICCAD (1993)
Wern-Jieh Sun, Carl Sechen
Efficient and effective placement for very large circuits. ICCAD (1993)
William Swartz, Carl Sechen
A new generalized row-based global router. ICCAD (1993)
Dahe Chen, Carl Sechen
Mickey: a macro cell global router. EURO-DAC (1991)
Kai-Win Lee, Carl Sechen
A global router for sea-of-gates circuits. EURO-DAC (1991)
William Swartz, Carl Sechen
New Algorithms for the Placement and Routing of Macro Cells. ICCAD (1990)
Carl Sechen, Dahe Chen
An improved objective function for mincut circuit partitioning. ICCAD (1988)
Carl Sechen
Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing. DAC (1988)
Kai-Win Lee, Carl Sechen
A new global router for row-based layout. ICCAD (1988)
Carl Sechen, Alberto L. Sangiovanni-Vincentelli
TimberWolf3.2: a new standard cell placement and global routing package. DAC (1986)