Jeyavijayan (JV) Rajendran

Publication Activity (10 Years)

Years Active: 2016-2023
Publications (10 Years): 18

Top Topics

Security Threats

Reinforcement Learning

Intellectual Property Protection

Top Venues

Publications

Hao Guo, Sayandeep Saha, Vasudev Gohil, Satwik Patnaik, Debdeep Mukhopadhyay, Jeyavijayan (JV) Rajendran
ExploreFault: Identifying Exploitable Fault Models in Block Ciphers with Reinforcement Learning. DAC (2023)
Hao Guo, Sayandeep Saha, Satwik Patnaik, Vasudev Gohil, Debdeep Mukhopadhyay, Jeyavijayan (JV) Rajendran
Vulnerability Assessment of Ciphers To Fault Attacks Using Reinforcement Learning. IACR Cryptol. ePrint Arch. 2022 (2022)
Satwik Patnaik, Vasudev Gohil, Hao Guo, Jeyavijayan (JV) Rajendran
Reinforcement Learning for Hardware Security: Opportunities, Developments, and Challenges. ISOCC (2022)
Vasudev Gohil, Satwik Patnaik, Hao Guo, Dileep Kalathil, Jeyavijayan (JV) Rajendran
DETERRENT: detecting trojans using reinforcement learning. DAC (2022)
Siddharth Garg, Daniel E. Holcomb, Jeyavijayan (JV) Rajendran, Ahmad-Reza Sadeghi
Guest Editors' Introduction: Competing to Secure SoCs. IEEE Des. Test 38 (1) (2021)
Zhaokun Han, Muhammad Yasin, Jeyavijayan (JV) Rajendran
Does logic locking work with EDA tools? USENIX Security Symposium (2021)
Zhaokun Han, Muhammad Yasin, Jeyavijayan (JV) Rajendran
Multi-Objective Strategies for Stripped-Functionality Logic Locking. ISCAS (2020)
Adriana C. Sanabria-Borbon, Nithyashankari Gummidipoondi Jayasankaran, S. Y. Lee, Edgar Sánchez-Sinencio, J. Hu, Jeyavijayan (JV) Rajendran
Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated Circuits. ITC (2020)
Hassan Salmani, Tamzidul Hoque, Swarup Bhunia, Muhammad Yasin, Jeyavijayan (JV) Rajendran, Naghmeh Karimi
Special Session: Countering IP Security threats in Supply chain. VTS (2019)
Muhammad Yasin, Chongzhi Zhao, Jeyavijayan (JV) Rajendran
SFLL-HLS: Stripped-Functionality Logic Locking Meets High-Level Synthesis. ICCAD (2019)
Monir Zaman, Abhrajit Sengupta, Danqing Liu, Ozgur Sinanoglu, Yiorgos Makris, Jeyavijayan (JV) Rajendran
Towards provably-secure performance locking. DATE (2018)
Yujie Wang, Pu Chen, Jiang Hu, Jeyavijayan (JV) Rajendran
Routing perturbation for enhanced security in split manufacturing. ASP-DAC (2017)
Jeyavijayan (JV) Rajendran
An overview of hardware intellectual property protection. ISCAS (2017)
Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu
TTLock: Tenacious and traceless logic locking. HOST (2017)
Thomas Broadfoot, Carl Sechen, Jeyavijayan (JV) Rajendran
On designing optimal camouflaged layouts. HOST (2017)
Muhammad Yasin, Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu, Ramesh Karri
On Improving the Security of Logic Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (9) (2016)
Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu, Ramesh Karri
Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach. IEEE Trans. Very Large Scale Integr. Syst. 24 (9) (2016)
Muhammad Yasin, Bodhisatwa Mazumdar, Jeyavijayan (JV) Rajendran, Ozgur Sinanoglu
SARLock: SAT attack resistant logic locking. HOST (2016)