Louis Scheffer

Publication Activity (10 Years)

Years Active: 1985-2014
Publications (10 Years): 0

Top Topics

Primary Visual Cortex

Learning Problems

Top Venues

Publications

Toufiq Parag, Stephen Plaza, Louis Scheffer
Small Sample Learning of Superpixel Classifiers for EM Segmentation- Extended Version. CoRR (2014)
Toufiq Parag, Stephen M. Plaza, Louis Scheffer
Small Sample Learning of Superpixel Classifiers for EM Segmentation. MICCAI (1) (2014)
Louis Scheffer
Lessons from the neurons themselves. ASP-DAC (2014)
Louis Scheffer
Design tools for artificial nervous systems. DAC (2012)
Patrick Groeneveld, Louis Scheffer, Dirk Stroobandt
SLIP: 10 years ago and 10 years from now. SLIP (2010)
Louis Scheffer
Physical design of biological systems. ISPD (2010)
David T. Blaauw, Kaviraj Chopra, Ashish Srivastava, Louis Scheffer
Statistical Timing Analysis: From Basic Principles to State of the Art. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (4) (2008)
David Cross, Eric Nequist, Louis Scheffer
A DFM aware, space based router. ISPD (2007)
Louis Scheffer
CAD Implications of New Interconnect Technologies. DAC (2007)
Igor L. Markov, Louis Scheffer, Dirk Stroobandt
Special issue on System-Level Interconnect Prediction. Integr. 40 (4) (2007)
Louis Scheffer, Lars Liebmann, Riko Rakojcic, David White
Rules vs tools: what's the right way to address IC manufacturing complexity? ISPD (2007)
Louis Scheffer
An overview of on-chip interconnect variation. SLIP (2006)
Richard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah
Is statistical timing statistically significant? DAC (2004)
Desmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester
The great interconnect buffering debate: are you a chicken or an ostrich? ISPD (2004)
Louis Scheffer
Physical CAD changes to incorporate design for lithography and manufacturability. ASP-DAC (2004)
Louis Scheffer
Some conditions under which hierarchical verification is O(N). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (5) (2003)
Louis Scheffer
Signal Integrity and Power Supply Network Analysis of Deep SubMicron Chips. PATMOS (2003)
Andrew B. Kahng, Shekhar Borkar, John M. Cohn, Antun Domic, Patrick Groeneveld, Louis Scheffer, Jean-Pierre Schoellkopf
Nanometer design: place your bets. DAC (2003)
Louis Scheffer
Methodologies and Tools for Pipelined On-Chip Interconnect. ICCD (2002)
Louis Scheffer
Explicit computation of performance as a function of process variation. Timing Issues in the Specification and Synthesis of Digital Systems (2002)
Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen
Timing- and crosstalk-driven area routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20 (4) (2001)
Andrew B. Kahng, Bing J. Sheu, Nancy Nettleton, John M. Cohn, Shekhar Borkar, Louis Scheffer, Ed Cheng, Sang Wang
Panel: Is Nanometer Design Under Control? DAC (2001)
Raul Camposano, Jacob Greidinger, Patrick Groeneveld, Michael Jackson, Lawrence T. Pileggi, Louis Scheffer
Design closure (panel session): hope or hype? DAC (2000)
Louis Scheffer, Eric Nequist
Why interconnect prediction doesn't work. SLIP (2000)
Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen
Timing and Crosstalk Driven Area Routing. DAC (1998)
Louis Scheffer
A roadmap of CAD tool changes for sub-micron interconnect problems. ISPD (1997)
Louis Scheffer, Ronny Soetarman
Hierarchical analysis of IC artwork with user defined abstraction rules. DAC (1985)