Chandramouli Visweswariah

Publication Activity (10 Years)

Years Active: 1988-2006
Publications (10 Years): 0

Publications

Chandramouli Visweswariah, K. Ravindran, Kerim Kalafala, Steven G. Walker, S. Narayan, Daniel K. Beece, Jeff Piaget, Natesan Venkateswaran, Jeffrey G. Hemmett
First-Order Incremental Block-Based Statistical Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (10) (2006)
Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (11) (2006)
Andreas Wächter, Chandramouli Visweswariah, Andrew R. Conn
Large-scale nonlinear optimization in circuit tuning. Future Gener. Comput. Syst. 21 (8) (2005)
Chandramouli Visweswariah, K. Ravindran, Kerim Kalafala, Steven G. Walker, S. Narayan
First-order incremental block-based statistical timing analysis. DAC (2004)
Richard Goldman, Kurt Keutzer, Clive Bittlestone, Ahsan Bootehsaz, Shekhar Y. Borkar, E. Chen, Louis Scheffer, Chandramouli Visweswariah
Is statistical timing statistically significant? DAC (2004)
Jochen A. G. Jess, Kerim Kalafala, Srinath R. Naidu, Ralph H. J. M. Otten, Chandramouli Visweswariah
Statistical timing for parametric yield prediction of digital integrated circuits. DAC (2003)
Xiaoliang Bai, Chandramouli Visweswariah, Philip N. Strenski
Uncertainty-aware circuit optimization. DAC (2002)
Andrew R. Conn, Chandramouli Visweswariah
Overview of continuous optimization advances and applications to circuit tuning. ISPD (2001)
Chandramouli Visweswariah, Ruud A. Haring, Andrew R. Conn
Noise considerations in circuit optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (6) (2000)
Andrew R. Conn, Ibrahim M. Elfadel, W. W. Molzen, P. R. O'Brien, Philip N. Strenski, Chandramouli Visweswariah, C. B. Whan
Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation. DAC (1999)
Chandramouli Visweswariah, Andrew R. Conn
Formulation of static circuit optimization with reduced size, degeneracy and redundancy by timing graph manipulation. ICCAD (1999)
Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah
Noise considerations in circuit optimization. ICCAD (1998)
Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah, Chai Wah Wu
JiffyTune: circuit optimization using time-domain sensitivities. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (12) (1998)
Andrew R. Conn, Ruud A. Haring, Chandramouli Visweswariah, Chai Wah Wu
Circuit optimization via adjoint Lagrangians. ICCAD (1997)
Chandramouli Visweswariah
Optimization techniques for high-performance digital circuits. ICCAD (1997)
Andrew R. Conn, Paula K. Coulman, Ruud A. Haring, Gregory L. Morrill, Chandramouli Visweswariah
Optimization of custom MOS circuits by transistor sizing. ICCAD (1996)
Daniel Brand, Chandramouli Visweswariah
Inaccuracies in power estimation during logic synthesis. ICCAD (1996)
Chandramouli Visweswariah, Jalal A. Wehbeh
Incremental Event-Driven Simulation of Digital FET Circuits. DAC (1993)
Rakesh Chadha, Chandramouli Visweswariah, Chin-Fu Chen
-a multilevel mixed-mode mixed A/D simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11 (5) (1992)
Chandramouli Visweswariah, Ronald A. Rohrer
Efficient Simulation of Bipolar Digital ICs. DAC (1991)
Chandramouli Visweswariah, Ronald A. Rohrer
Piecewise approximate circuit simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (7) (1991)
Chandramouli Visweswariah, Peter Feldmann, Ronald A. Rohrer
Incorporation of Inductors in Piecewise Approximate Circuit Simulation. ICCAD (1990)
Chandramouli Visweswariah, Ronald A. Rohrer
Piecewise approximate circuit simulation. ICCAD (1989)
Chandramouli Visweswariah, Rakesh Chadha, Chin-Fu Chen
Model Development and Verification for High Level Analog Blocks. DAC (1988)